Datasheet

Chapter 14. UART Modules 14-1
Chapter 14
UART Modules
This chapter describes the use of the universal asynchronous/synchronous
receiver/transmitters (UARTs) implemented on the MCF5307 and includes programming
examples. All references to UART refer to one of these modules.
14.1 Overview
The MCF5307 contains two independent UARTs. Each UART can be clocked by BCLKO,
eliminating the need for an external crystal. As Figure 14-1 shows, each UART module
interfaces directly to the CPU and consists of the following:
• Serial communication channel
• Programmable transmitter and receiver clock generation
• Internal channel control logic
• Interrupt control logic
Figure 14-1. Simplified Block Diagram
The serial communication channel provides a full-duplex asynchronous/synchronous
receiver and transmitter deriving an operating frequency from BCLKO or an external clock
using the timer pin. The transmitter converts parallel data from the CPU to a serial bit
stream, inserting appropriate start, stop, and parity bits. It outputs the resulting stream on
the channel transmitter serial data output (TxD). See Section 14.5.2.1, “Transmitting.”
The receiver converts serial data from the channel receiver serial data input (RxD) to
parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers
the assembled character onto the bus during read operations. The receiver may be polled-
or interrupt-driven. See Section 14.5.2.2, “Receiver.”
Serial
Interrupt Control
Logic
CTS
RTS
RxD
TxD
or
External clock (TIN)
Internal Channel
Control Logic
Programmable
Clock
Communications
Channel
Generation
System Integration
Module (SIM)
Interrupt
Controller
UART
BCLKO
Fr
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Freescale Semiconductor, Inc.
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