Datasheet

Chapter 14. UART Modules 14-3
Register Descriptions
Table 14-1. UART Module Programming Model
MBAR Offset
[31:24] [23:16] [15:8] [7:0]
UART0 UART1
0x1C0 0x200 UART mode
registers
1
—(UMR1n)
[p. 14-4], (UMR2n) [p.
14-6]
—
0x1C4 0x204 (Read) UART status
registers—(USRn) [p.
14-7]
—
(Write) UART
clock-select
register
1
—(UCSRn)
[p. 14-8]
—
0x1C8 0x208 (Read) Do not access
2
—
(Write) UART
command
registers—(UCRn) [p.
14-9]
—
0x1CC 0x20C (UART/Read) UART
receiver
buffers—(URBn) [p.
14-11]
—
(UART/Write) UART
transmitter
buffers—(UTBn) [p.
14-11]
—
0x1D0 0x210 (Read) UART input
port change
registers—(UIPCRn)
[p. 14-12]
—
(Write) UART auxiliary
control
registers
1
—(UACRn)
[p. 14-12]
—
0x1D4 0x214 (Read) UART interrupt
status
registers—(UISRn) [p.
14-13]
—
(Write) UART interrupt
mask
registers—(UIMRn) [p.
14-13]
—
0x1D8 0x218 UART divider upper
registers—(UDUn) [p.
14-14]
—
0x1DC 0x21C UART divider lower
registers—(UDLn) [p.
14-14]
—
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eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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