Datasheet

Chapter 14. UART Modules 14-11
Register Descriptions
14.3.6 UART Receiver Buffers (URBn)
The receiver buffers contain one serial shift register and three receiver holding registers,
which act as a FIFO. RxD is connected to the serial shift register. The CPU reads from the
top of the stack while the receiver shifts and updates from the bottom when the shift register
is full (see Figure 14-20). RB contains the character in the receiver.
14.3.7 UART Transmitter Buffers (UTBn)
The transmitter buffers consist of the transmitter holding register and the transmitter shift
register. The holding register accepts characters from the bus master if channel’s
USRn[TxRDY] is set. A write to the transmitter buffer clears TxRDY, inhibiting any more
characters until the shift register can accept more data. When the shift register is empty, it
checks if the holding register has a valid character to be sent (TxRDY = 0). If there is a valid
character, the shift register loads it and sets USRn[TxRDY] again. Writes to the transmitter
buffer when the channel’s TxRDY = 0 and when the transmitter is disabled have no effect
on the transmitter buffer.
Figure 14-8 shows UTB0. TB contains the character in the transmitter buffer.
1–0
RC (This field selects a single command)
00
NO ACTION TAKEN Causes the receiver to stay in its current mode. If the receiver is enabled, it
remains enabled; if disabled, it remains disabled.
01
RECEIVER ENABLE If the UART module is not in multidrop mode (UMR1n[PM] ≠ 11), RECEIVER
ENABLE enables the channel's receiver and forces it into search-for-start-bit state.
If the receiver is already enabled, this command has no effect.
10
RECEIVER DISABLE Disables the receiver immediately. Any character being received is lost. The
command does not affect receiver status bits or other control registers. If the
UART module is programmed for local loop-back or multidrop mode, the receiver
operates even though this command is selected. If the receiver is already
disabled, the command has no effect.
11 — Reserved, do not use.
7 0
Field RB
Reset 0000_0000
R/W Read only
Address MBAR + 0x1CC,0x20C
Figure 14-7. UART Receiver Buffer (URB0)
Table 14-6. UCRn Field Descriptions (Continued)
Bits Value Command Description
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