Datasheet

14-12 MCF5307 User’s Manual
Register Descriptions
14.3.8 UART Input Port Change Registers (UIPCRn)
The input port change registers (UIPCRn), Figure 14-9, hold the current state and the
change-of-state for CTS
.
Table 14-7 describes UIPCRn fields.
14.3.9 UART Auxiliary Control Register (UACRn)
The UART auxiliary control registers (UACRn), Figure 14-7, control the input enable.
7 0
Field TB
Reset 0000_0000
R/W Write only
Address MBAR + 0x1CC,0x20C
Figure 14-8. UART Transmitter Buffer (UTB0)
7 543 10
Field — COS 111 CTS
Reset 0000 0 11 CTS
R/W Read only
Address MBAR + 0x1D0 (UIPCR0), 0x210 (UIPCR1)
Figure 14-9. UART Input Port Change Register (UIPCRn)
Table 14-7. UIPCRn Field Descriptions
Bits Name Description
7–5 — Reserved, should be cleared.
4 COS Change of state (high-to-low or low-to-high transition).
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS].
1 A change-of-state longer than 25–50 µs occurred on the CTS
input. UACRn can be programmed to
generate an interrupt to the CPU when a change of state is detected.
3–1 — Reserved, should be cleared.
0 CTS Current state. Starting two serial clock periods after reset, CTS reflects the state of CTS
. If CTS is
detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled.
0 The current state of the CTS
input is asserted.
1 The current state of the CTS
input is negated.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...