Datasheet

Chapter 14. UART Modules 14-15
Register Descriptions
14.3.12 UART Interrupt Vector Register (UIVRn)
The UIVRn, Figure 14-14, contain the 8-bit internal interrupt vector number (IVR).
Table 14-10 describes UIVRn fields.
14.3.13 UART Input Port Register (UIPn)
The UART input port registers (UIPn), Figure 14-15, show the current state of the CTS
input.
Table 14-11 describes UIPn fields.
14.3.14 UART Output Port Command Registers
(UOP1n/UOP0n)
In UART mode, the RTS output can be asserted by writing a 1 to UOP1n[RTS] and negated
by writing a 1 to UOP0n[RTS]. See Figure 14-16.
7 0
Field IVR
Reset 0000_1111
R/W R/W
Address MBAR + 0x1F0 (UIVR0), 0x230 (UIVR1)
Figure 14-14. UART Interrupt Vector Register (UIVRn)
Table 14-10. UIVRn Field Descriptions
Bits Name Description
7–0 IVR Interrupt vector. Indicates the vector number where the address of the exception handler for the
specified interrupt is located. UIVRn is reset to 0x0F, indicating an uninitialized interrupt condition.
7 10
Field — CTS
Reset 1111_1111
R/W Read only
Address MBAR + 0x1F4 (UIP0), 0x234 (UIP1)
Figure 14-15. UART Input Port Register (UIPn)
Table 14-11. UIPn Field Descriptions
Bits Name Description
7–1 — Reserved, should be cleared.
0 CTS Current state. The CTS
value is latched and reflects the state of the input pin when UIPn is read.
Note: This bit has the same function and value as UIPCRn[RTS].
0 The current state of the CTS
input is logic 0.
1 The current state of the CTS
input is logic 1.
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