Datasheet

Chapter 17. Signal Descriptions 17-15
Chip-Select Module Signals
of memory if desired. ADDR_CONFIG is multiplexed with D4 and its configuration is
sampled at reset as shown in Table 17-14.
17.5.7 D[3:2]—Frequency Control PLL (FREQ[1:0])
The frequency control PLL input bus (FREQ[1:0]) indicates the CLKIN frequency range.
These signals are multiplexed with D[3:2] and are sampled during the assertion of RESET
.
These signals indicate the operating frequency range to the PLL, as shown in Table 17-15.
Note that these signals do not affect the PLL frequency but are required to set up the analog
PLL.
17.5.8 D[1:0]—Divide Control PCLK to BCLKO (DIVIDE[1:0])
This 2-bit input bus indicates the BCLKO/PSTCLK ratio. These signals are sampled during
the assertion of RESET
and indicate the ratios shown in Table 17-16.
17.6 Chip-Select Module Signals
The MCF5307 device provides eight programmable chip-select signals that can directly
interface with SRAM, EPROM, EEPROM, and peripherals. These signals are asserted and
negated on the falling edge of the clock.
Table 17-14. D4/ADDR_CONFIG, Address Pin Assignment
D4/ADDR_CONFIG PAR Configuration at Reset
0 PP[15:0], defaulted to inputs upon reset
1 A[31:24]/TIP/DREQ[1:0]/TM[2:0]/TT[1:0]
Table 17-15. CLKIN Frequency
FREQ[1:0]/D[3:2] CLKIN Frequency (MHz)
00 16.6–27.999
01 28–38.999
10 39–45
11 Reserved
Table 17-16. BCLKO/PSTCLK Divide Ratios
DIVIDE[1:0]/D[1:0] Ratio of BCLKO/PSTCLK
00 1/4
01 Reserved
10 1/2
11 1/3
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