Datasheet

17-18 MCF5307 User’s Manual
Serial Module Signals
17.8.1 DMA Request (DREQ[1:0]/PP[6:5])
The DMA request pins (DREQ[1:0]/PP[6:5]) can serve as the DMA request inputs or as
two bits of the parallel port, as determined by individually programmable bits in the PAR.
These inputs are asserted by a peripheral device to request an operand transfer between that
peripheral and memory by either channel 0 or 1 of the on-chip DMA.
Note that DMA acknowledge indication is displayed on TM[2:0], during DMA transfers of
channel 0 and 1.
17.9 Serial Module Signals
The signals in the following sections are used to transfer serial data between the two UART
modules and external peripherals.
17.9.1 Transmitter Serial Data Output (TxD)
TxD is held high (mark condition) when the transmitter is disabled, idle, or operating in the
local loop-back mode. Data is shifted out least-significant bit (lsb) first on TxD on the
falling edge of the clock source.
17.9.2 Receiver Serial Data Input (RxD)
Data received on RxD is sampled on the rising edge of the clock source, with the lsb
received first.
17.9.3 Clear to Send (CTS)
This input can generate an interrupt on a change of state.
17.9.4 Request to Send (RTS)
This output can be programmed to be negated or asserted automatically by either the
receiver or the transmitter. When connected to a transmitter’s CTS
, RTS can control serial
data flow.
17.10 Timer Module Signals
The signals in the following sections are external interfaces to the two general-purpose
MCF5307 timers. These 16-bit timers can capture timer values, trigger external events or
internal interrupts, or count external events.
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Freescale Semiconductor, Inc.
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