Datasheet

Chapter 17. Signal Descriptions 17-19
Parallel I/O Port (PP[15:0])
17.10.1 Timer Inputs (TIN[1:0])
TIN[1:0] can be programmed as clocks that cause events in the counter and prescalers.
They can also cause captures on the rising edge, falling edge, or both edges.
17.10.2 Timer Outputs (TOUT1, TOUT0)
The programmable timer outputs (TOUT1 and TOUT0) pulse or toggle on various timer
events.
17.11 Parallel I/O Port (PP[15:0])
This 16-bit bus is dedicated for general-purpose I/O. The parallel port is multiplexed with
the A[31:24], TT[1:0], TM[2:0], TIP
, and DREQ[1:0]. These 16 bits are programmed for
functionality with the PAR in the SIM.
The system designer controls the reset value of this register by driving D4 with a 1 or 0 on
the rising edge of RSTI
(reset input to MCF5307 device). At reset, the system is configured
as PP[15:0] if D4 is 0; otherwise alternate pin functions selected by PAR = 1 are used.
Motorola recommends that D4 be driven during reset to a logic level.
17.12 I
2
C Module Signals
The I
2
C module acts as a two-wire, bidirectional serial interface between the MCF5307 and
peripherals with an I
2
C interface (such as LED controller, A-to-D converter, or D-to-A
converter). Devices connected to the I
2
C must have open-drain or open-collector outputs.
17.12.1 I
2
C Serial Clock (SCL)
The bidirectional, open-drain I
2
C serial clock signal (SCL) is the clock signal for I
2
C
module operation. The I
2
C module controls this signal when the bus is in master mode; all
I
2
C devices drive this signal to synchronize I
2
C timing.
17.12.2 I
2
C Serial Data (SDA)
The bidirectional, open-drain I
2
C serial data signal (SDA) is the data input/output for the
serial I
2
C interface.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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