Datasheet

18-4 MCF5307 User’s Manual
Data Transfer Operation
Figure 18-2. Connections for External Memory Port Sizes
The timing relationships between BCLKOchip select (CS[7:0]), byte enable/byte write
enables (BE
/BWE[3:0]), and output enable (OE) are similar to their relationships with
address strobe (AS
) in that all transitions occur during the low phase of BCLKO. However,
as shown in Figure 18-3, differences in on-chip signal routing and external loading may
prevent signals from asserting simultaneously.
Figure 18-3. Chip-Select Module Output Timing Diagram
18.4.1 Bus Cycle Execution
When a bus cycle is initiated, the MCF5307 first compares its address with the base address
and mask configurations programmed for chip selects 0–7 (CSCR0–CSCR7) and for
DRAM blocks 0 and 1 address and control registers (DACR0 and DACR1). If the driven
address matches a programmed chip select or DRAM block, the appropriate chip select is
asserted or the DRAM block is selected using the specifications programmed in the
respective configuration register. Otherwise, the following occurs:
• If the address and attributes do not match in CSCR or DACR, the MCF5307 runs an
external burst-inhibited bus cycle with a default of external termination on a 32-bit
port.
• If an address and attribute match in multiple CSCRs, the matching chip-select
signals are driven; however, the MCF5307 runs an external burst-inhibited bus cycle
with external termination on a 32-bit port.
• If an address and attribute match both DACRs or a DACR and a CSCR, the operation
is undefined.
Processor
Data Bus
Byte 0
8-Bit Port
16-Bit Port
32-Bit Port
Byte 1
Byte 2
Byte 3
Byte 0 Byte 1
Byte 2 Byte 3
Byte 0 Byte 1 Byte 2 Byte 3
D[31:24] D[23:16] D[15:8] D[7:0]
External
Memory
Memory
Memory
Byte Enable BE0
BE1 BE2 BE3
Driven with
indeterminate values
Driven with
indeterminate values
CS[7:0]
BCLKO
BE/BWE[3:0]
AS, OE
Fr
eescale S
emiconduct
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, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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