Datasheet

Chapter 18. Bus Operation 18-5
Data Transfer Operation
Table 18-3 shows the type of access as a function of match in the CSCRs and DACRs.
Basic bus operations occur in three clocks, as follows:
1. During the first clock, the address, attributes, and TS
are driven. AS is asserted at the
falling edge of the clock to indicate that address and attributes are valid and stable.
2. Data and T
A are sampled during the second clock of a bus-read cycle. During a read,
the external device provides data and is sampled at the rising edge at the end of the
second bus clock. This data is concurrent with T
A, which is also sampled at the
rising clock edge.
During a write, the MCF5307 drives data from the rising clock edge at the end of the
first clock to the rising clock edge at the end of the bus cycle. Wait states can be
added between the first and second clocks by delaying the assertion of T
A. TA can
be configured to be generated internally through the DACRs and CSCRs. If T
A is
not generated internally, the system must provide it externally.
3. The last clock of the bus cycle uses what would be an idle clock between cycles to
provide hold time for address, attributes, and write data. Figure 18-6 and
Figure 18-8 show the basic read and write operations.
18.4.2 Data Transfer Cycle States
The data transfer operation in the MCF5307 is controlled by an on-chip state machine. Each
bus clock cycle is divided into two states. Even states occur when BCLKO is high and odd
states occur when BCLKO is low. The state transition diagram for basic and
fast-termination read and write cycles is shown in Figure 18-4.
Table 18-3. Accesses by Matches in CSCRs and DACRs
Number of CSCR Matches Number of DACR Matches Type of Access
0 0 External
10 Defined by CSCRs
Multiple 0 External, burst-inhibited, 32-bit
01 Defined by DACRs
1 1 Undefined
Multiple 1 Undefined
0 Multiple Undefined
1 Multiple Undefined
Multiple Multiple Undefined
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