Datasheet

1-2 MCF5307 User’s Manual
Features
Figure 1-1. MCF5307 Block Diagram
DRAM Controller Chip-Select Module External
Bus Interface
Software
Watchdog
Two
Two UARTs
DMA
I
2
C Module
JTAG
Debug
MAC
V3 COLDFIRE PROCESSOR COMPLEX
SYSTEM INTEGRATION MODULE (SIM)
8-Kbyte
Cache
SRAM Controller
DIV
Eight-Instruction
FIFO Buffer
Operand Execution
Pipeline (OEP)
Instruction Fetch
Pipeline (IFP)
Branch Logic
32-Bit Data Bus
4-Entry
Store
Buffer
31 0
Four
32-Bit Address Bus
CCR
General-
Purpose
31 0
31 0
A0–A7
D0–D7
IED
IAG
IC1
IC2
DSOC
AGEX
Interrupt Controller
Local Memory Bus
PLL
CLKIN
RSTI
PSTCLK
RSTO
PCLK
BCLKO
X n
Module
CS[7:0]
888
8
10 ICRs
MBAR
IMR
Channels
General-
Purpose
Timers
(sent off-chip
Cache Controller
ACR0
ACR1
CACR
CSARs CSCRs CSMRs
IRQ
[1,3,5,7]
4
DRAM Controller
AVR
IPR
IRQPAR
SWIVR
SWSR SYPCR
RSR
System Control PLL Control
PLL
Base Address
MPARK
Bus Master Park
DMR0/1
DACR0/1
Addr/Cntrl Mask
DRAM Control
DCR
Parallel Port
PLL
Control Signals
Outputs
4-Kbyte
SRAM
RAMBAR
and to on-chip
peripherals)
Local
Instruction Unit
Registers
Memory
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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