Datasheet

18-36 MCF5307 User’s Manual
Reset Operation
Figure 18-34. Software Watchdog Reset Timing
During the software watchdog reset period, all signals that can be are driven to a
high-impedance state; all those that cannot be are negated. When RST
O negates, bus
signals remain in a high-impedance state until the MCF5307 is granted the bus and the
ColdFire core begins the first bus cycle for reset exception processing.
100K CLKIN
D[7:0] latched
>80 CLKIN
BCLKO
CLKIN
RSTI
BCLKO
BCLKO
PSTCLK
RSTO
30 BCLKO
20 BCLKO
15 BCLKO
(1/2 MODE)
(1/3 MODE)
(1/4 MODE)
D[7:0]
Cycle Lock Time
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...