Datasheet

20-4 MCF5307 User’s Manual
Input/Output AC Timing Specifications
Table 20-6 lists specifications for timings in Figure 20-3, Figure 20-4, and Figure 20-10.
Although output signals that share a specification number have approximately the same
timing, due to loading differences, they do not necessarily change at the same time.
However, they have similar timings; that is, minimum and maximum times are not mixed.
Note that these figures show two representative bus operations and do not attempt to show
all cases. For explanations of the states, S0–S5, see Section 18.4, “Data Transfer
B5
3
BCLKO to input high impedance — 2 — 2 Bus clock
B6 BCLKO to EDGESEL delay 0 7.5 0 5.5 nS
1
Inputs: BG, TA, A[23:0], PP[15:0], SIZ[1:0], R/W, TS, EDGESEL, D[31:0], IRQ[7,5,3,1], and BKPT
2
Inputs: AS
3
Inputs: D[31:0]
Table 20-6. Output AC Timing Specification
Num Characteristic
66 MHz 90 MHz
Units
Min Max Min Max
B10
1,2,3
1
Outputs that only change on rising edge of BCLKO: RSTO, TS, BR, BD, TA, R/W, SIZ[1:0], PP[7:0] (and
PP[15:8] when configured as parallel port outputs).
2
Outputs that can change on either BCLKO edge depending only upon EDGESEL: D[31:0], A[23:0], SCKE,
SRAS
, SCAS, DRAMW (and PP[15:8] when individually configured as address outputs).
3
Outputs that can change on either BCLKO edge depending only upon EDGESEL: D[31:0], A[23:0], SCKE,
SRAS
, SCAS, DRAMW (and PP[15:8] when individually configured as address outputs).
BCLKO rising to valid — 15 — 11 nS
B11
1,2,3,4
4
Applies to D[31:0], A[23:0], RSTO, TS, BR, BD, TA, R/W, SIZ[1:0], PP[7:0] (and PP[15:8] when configured as
parallel port outputs).
BCLKO rising to invalid (hold) 1 — 1 — nS
B11a
1,2,3,5
5
Applies to RAS[1:0], CAS[1:0], SCKE, SRAS, SCAS, DRAMW
BCLKO rising to invalid (hold) 0.5 — 0.5 —
B12
6,7
6
High Impedance (three-state): D[31:0]
7
Outputs that transition to high-impedance due to bus arbitration: A[23:0], R/W, SIZ[1:0], TS, AS, TA, (and
PP[15:0] when individually configured as address outputs)
BCLKO to high impedance (three-state) — 15 — 11 nS
B13
8,2,3
8
Outputs that only change on falling edge of BCLKO: AS, CS[7:0], BE[3:0], OE
BCLKO rising to valid — 15 — 11 nS
B14
8,2,3
BCLKO rising to invalid (hold) 3 — 2 — nS
B15
2,3
EDGESEL to valid — 18.5 — 13.5 nS
B16
2,3
EDGESEL to invalid (hold) 3 — 2 — nS
H1 HIZ
to high impedance — 60 — 60 nS
H2 HIZ
to low Impedance — 60 — 60 nS
Table 20-5. Input AC Timing Specification
Num Characteristic
66 MHz 90 MHz
Units
Min Max Min Max
Fr
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Freescale Semiconductor, Inc.
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