Datasheet

Chapter 20. Electrical Specifications 20-7
Input/Output AC Timing Specifications
Figure 20-5. SDRAM Write Cycle with EDGESEL Tied to Buffered BCLKO
Figure 20-6 shows an SDRAM read cycle with EDGESEL tied high.
A[31:0]
TS
SRAS
SCAS
1
D[31:0]
ACTV PALL
NOP
RAS
WRITE
Row Column
EDGESEL
DRAMW
CAS
B16
B15
B15
B16
B16
B16
0
1 2 3 4 5 6 7 8 9 10 11 12
BCLKO
B15
1
DACR[CASL] = 2
B6
NOP
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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