Datasheet

20-8 MCF5307 User’s Manual
Input/Output AC Timing Specifications
Figure 20-6. SDRAM Read Cycle with EDGESEL Tied High
Figure 20-7 shows an SDRAM write cycle with EDGESEL tied high.
A[31:0]
TS
SRAS
D[31:0]
ACTV NOP PALLNOP
RAS
READ
Row Column
BCLKO
0
DRAMW
CAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
B11
B10
B10
B11a
B2
B1
B11a
B11a
1
DACR[CASL] = 2
SCAS
1
NOP
B11a
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...