Datasheet

20-12 MCF5307 User’s Manual
Reset Timing Specifications
20.4 Reset Timing Specifications
Table 20-7 lists specifications for the reset timing parameters shown in Figure 20-11.
Figure 20-11 shows reset timing for the values in Table 20-7.
Figure 20-11. Reset Timing
20.5 Debug AC Timing Specifications
Table 20-8 lists specifications for the debug AC timing parameters shown in Figure 20-13.
Table 20-7. Reset Timing Specification
Num Characteristic
66 MHz 90 MHz
Units
Min Max Min Max
R1
1
1
RSTI and D[7:0] are synchronized internally. Setup and hold times must be met
only if recognition on a particular clock is required.
Valid to CLKIN (setup) 7.5 — 5.5 — nS
R2 CLKIN to invalid (hold) 3 — 2 — nS
R3 RSTI
to invalid (hold) 3 — 2 — nS
Table 20-8. Debug AC Timing Specification
Num Characteristic
66 MHz 90 MHz
Units
Min Max Min Max
D1 PST, DDATA to PSTCLK setup 7.5 5.5 nS
D2 PSTCLK to PST, DDATA hold 7.5 5.5 nS
D3
DSI-to-DSCLK setup 1 1 PSTCLKs
CLKIN
RSTI
D[7:0]
R2
R1
R1
R3
Note: Mode selects are registered on the rising CLKIN edge before the cycle in which RSTI
is
recognized as being negated.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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