Datasheet

Appendix A. List of Memory Maps A-5
(Write) UART auxiliary
control
registers
1
—(UACRn)
[p. 14-12]
—
0x1D4 (Read) UART interrupt
status registers—(UISRn)
[p. 14-13]
—
(Write) UART interrupt
mask registers—(UIMRn)
[p. 14-13]
—
0x1D8 UART divider upper
registers—(UDUn)
[p. 14-14]
—
0x1DC UART divider lower
registers—(UDLn)
[p. 14-14]
—
0x1E0–
0x1EC
Do not access
2
—
0x1F0 UART interrupt vector
register—(UIVRn)
[p. 14-15]
—
0x1F4 (Read) UART input port
registers—(UIPn)
[p. 14-15]
—
(Write) Do not access
2
—
0x1F8 (Read) Do not access
2
—
(Write) UART output port
bit set command
registers—(UOP1n
3
)
[p. 14-15]
—
0x1FC (Read) Do not access
2
—
(Write) UART output port
bit reset command
registers—(UOP0n
3
)
[p. 14-15]
—
1
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software
reset command. That is, if channel operation is not disabled, undesirable results may occur.
2
This address is for factory testing. Reading this location results in undesired effects and possible
incorrect transmission or reception of characters. Register contents may also be changed.
3
Address-triggered commands
Table A-6. UART0 Module Programming Model (Continued)
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
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eescale S
emiconduct
or
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