Datasheet

INDEX
Index Index-21
interrupt
control signals, 17-12
request, 17-12
JTAG, 19-2
parallel I/O port, 17-19
read/write, 17-8
reset in, out, 17-13
serial module
general, 17-18
receiver serial data input, 17-18
send, 17-18
transmitter serial data output, 17-18
size, 17-8
timer module, 17-18
transfer
acknowledge, 17-9
in progress, 17-10
modifier, 17-10
start, 17-9
Signals
overview, 17-1
SIM
features, 6-1
programming model, 6-3
register memory map, 6-3
Software watchdog
interrupt vector register, 6-9
service register, 6-9
timer, 6-6
STOP instruction, 5-4, 5-17
System protection control register, 6-8
T
Timer module
calculating time-out values, 13-7
capture registers, 13-4
code example, 13-6
counters, 13-5
event registers, 13-5
general-purpose programming model, 13-2
mode registers, 13-3
reference registers, 13-4
Timing
MAC unit instructions, 3-5
PLL, 7-4
RSTI, 7-5
Transfers generated internally, 6-12
U
UART modules
bus operation
interrupt acknowledge cycles, 14-28
read cycles, 14-28
write cycles, 14-28
clock source baud rates, 14-19
external clock, 14-19
FIFO stack in UART0, 14-24
initialization sequence, 14-29
looping modes, 14-25
automatic echo, 14-25
local loop-back, 14-25
remote loop-back, 14-26
mode registers, 14-4
multidrop mode, 14-26
programming, 14-28
receiver
enabled, 14-22
register description, 14-2
serial overview, 14-2
signal definitions, 14-16
transmitter/receiver
clock source, 14-18
modes, 14-19
transmitting in UART mode, 14-21
User programming model, 2-27
V
Variant address, 5-5
Vector base register, 2-30
W
WDDATA execution, 5-4
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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