Datasheet

2-22 MCF5307 User’s Manual

Features and Enhancements

2.1.1 Clock-Multiplied Microprocessor Core

The MCF5307 incorporates a clock-multiplying phase-locked loop (PLL). Increasing the

internal speed of the core also allows higher performance while providing the system

designer with an easy-to-use lower speed system interface.

The frequency of the processor complex can be 2x, 3x, or 4x the external bus speed.

The processor, cache, integrated SRAM, and misalignment module operate at the higher

speed clock (PCLK); other system integrated modules operate at the speed of the bus clock

(BCLKO). When combined with the enhanced pipeline structure of the Version 3 ColdFire

core, the processor and its local memories provide a high level of performance for today’s

demanding embedded applications.

PCLK can be disabled to minimize dissipation when a low-power mode is entered. This is

described in Section 7.2.3, “Reduced-Power Mode.”

2.1.2 Enhanced Pipelines

The IFP prefetches instructions. The OEP decodes instructions, fetches required operands,

then executes the speciﬁed function. The two independent, decoupled pipeline structures

maximize performance while minimizing core size. Pipeline stages are shown in Figure 2-1

and are summarized as follows:

• Four-stage IFP (plus optional instruction buffer stage)

— Instruction address generation (IAG) calculates the next prefetch address.

— Instruction fetch cycle 1 (IC1) initiates prefetch on the processor’s local

instruction bus.

— Instruction fetch cycle 2 (IC2) completes prefetch on the processor’s instruction

local bus.

— Instruction early decode (IED) generates time-critical decode signals needed for

the OEP.

— Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of

fetch latency.

• Two-stage OEP

— Decode, select/operand fetch (DSOC) decodes the instruction and selects the

required components for the effective address calculation, or the operand fetch

cycle.

— Address generation/execute (AGEX) Calculates the oeprand address, or

performs the execution of the instruction.

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Freescale Semiconductor, Inc.

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