Datasheet

2-26 MCF5307 User’s Manual
Programming Model
On-chip breakpoint resources include the following:
• Configuration/status register (CSR)
• Background debug mode (BDM) address attributes register (BAAR)
• Bus attributes and mask register (AATR)
• Breakpoint registers. These can be used to define triggers combining address, data,
and PC conditions in single- or dual-level definitions. They include the following:
— PC breakpoint register (PBR)
— PC breakpoint mask register (PBMR)
— Data operand address breakpoint registers (ABHR/ABLR)
— Data breakpoint register (DBR)
• Data breakpoint mask register (DBMR)
• Trigger definition register (TDR) can be programmed to generate a processor halt or
initiate a debug interrupt exception.
These registers can be accessed through the dedicated debug serial communication channel,
or from the processor’s supervisor programming model, using the WDEBUG instruction.
The enhancements of the Revision B debug specification are fully backward-compatible
with the A revision. For more information, see Chapter 5, “Debug Support.”
2.2 Programming Model
The MCF5307 programming model consists of three instruction and register groups—user,
MAC (also user-mode), and supervisor, shown in Figure 2-2. User mode programs are
restricted to user and MAC instructions and programming models. Supervisor-mode
system software can reference all user-mode and MAC instructions and registers and
additional supervisor instructions and control registers. The user or supervisor
programming model is selected based on SR[S]. The following sections describe the
registers in the user, MAC, and supervisor programming models.
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