Datasheet

Chapter 2. ColdFire Core 2-29
Programming Model
• Mask register (MASK)—This 16-bit general-purpose register provides an optional
address mask for MAC instructions that fetch operands from memory. It is useful in
the implementation of circular queues in operand memory.
• MAC status register (MACSR)—This 8-bit register defines configuration of the
MAC unit and contains indicator flags affected by MAC instructions. Unless noted
otherwise, MACSR indicator flag settings are based on the final result, that is, the
result of the final operation involving the product and accumulator.
2.2.2 Supervisor Programming Model
The MCF5307 supervisor programming model is shown in Figure 2-3. Typically, system
programmers use the supervisor programming model to implement operating system
functions and provide memory and I/O control. The supervisor programming model
provides access to the user registers and additional supervisor registers, which include the
upper byte of the status register (SR), the vector base register (VBR), and registers for
configuring attributes of the address space connected to the Version 3 processor core. Most
supervisor-mode registers are accessed by using the MOVEC instruction with the control
register definitions in Table 2-2.
2.2.2.1 Status Register (SR)
The SR stores the processor status, the interrupt priority mask, and other control bits.
Supervisor software can read or write the entire SR; user software can read or write only
SR[7–0], described in Section 2.2.1.5, “Condition Code Register (CCR).” The control bits
indicate processor states—trace mode (T), supervisor or user mode (S), and master or
interrupt state (M). SR is set to 0x27xx after reset.
1 V Overflow condition code bit. Set if an arithmetic overflow occurs, implying that the result cannot be
represented in the operand size; otherwise cleared.
0 C Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition or if a
borrow occurs in a subtraction; otherwise cleared.
Table 2-2. MOVEC Register Map
Rc[11–0] Register Definition
0x002 Cache control register (CACR)
0x004 Access control register 0 (ACR0)
0x005 Access control register 1 (ACR1)
0x801 Vector base register (VBR)
0xC04 RAM base address register (RAMBAR)
0xC0F Module base address register (MBAR)
Table 2-1. CCR Field Descriptions (Continued)
Bits Name Description
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