Datasheet

2-30 MCF5307 User’s Manual
Programming Model
Table 2-3 describes SR fields.
2.2.2.2 Vector Base Register (VBR)
The VBR holds the base address of the exception vector table in memory. The displacement
of an exception vector is added to the value in this register to access the vector table.
VBR[19–0] are not implemented and are assumed to be zero, forcing the vector table to be
aligned on a 0-modulo-1-Mbyte boundary.
2.2.2.3 Cache Control Register (CACR)
The CACR controls operation of both the instruction and data cache memory. It includes
bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining
the default cache mode and write-protect fields. See Section 4.10.1, “Cache Control
Register (CACR).”
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
System byte Condition code register (CCR)
Field T — S M — I P — X N Z V C
Reset 00100 111 0 00 —————
R/W R/W R R/W R/W R R/W R/W R R/W R/W R/W R/W R/W
Figure 2-5. Status Register (SR)
Table 2-3. Status Field Descriptions
Bits Name Description
15 T Trace enable. When T is set, the processor performs a trace exception after every instruction.
13 S Supervisor/user state. Indicates whether the processor is in supervisor or user mode
0 User mode
1 Supervisor mode
12 M Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution
of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer.
10–8 I Interrupt priority mask. Defines the current interrupt priority. Interrupt requests are inhibited for all
priority levels less than or equal to the current priority, except the edge-sensitive level-7 request,
which cannot be masked.
7–0 CCR Condition code register. See Table 2-1.
313029282726252423222120191817161514131211109876543210
Field Exception vector table base address —
Reset 0000_0000_0000_0000_0000_0000_0000_0000
R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from
the debug module only. The upper 12 bits are returned, the low-order 20 bits are undefined.
Rc[11–0] 0x801
Figure 2-6. Vector Base Register (VBR)
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