Datasheet

viii
MCF5307 User’s Manual
CONTENTS
Paragraph
Number
Title
Page
Number
4.9.5 Memory Accesses for Cache Maintenance................................................... 4-17
4.9.5.1 Cache Filling............................................................................................. 4-17
4.9.5.2 Cache Pushes ............................................................................................ 4-18
4.9.5.2.1 Push and Store Buffers ......................................................................... 4-18
4.9.5.2.2 Push and Store Buffer Bus Operation................................................... 4-18
4.9.6 Cache Locking.............................................................................................. 4-19
4.10 Cache Registers................................................................................................. 4-21
4.10.1 Cache Control Register (CACR) .................................................................. 4-21
4.10.2 Access Control Registers (ACR0–ACR1).................................................... 4-22
4.11 Cache Management........................................................................................... 4-24
4.12 Cache Operation Summary............................................................................... 4-25
4.12.1 Cache State Transitions ................................................................................ 4-25
4.13 Cache Initialization Code.................................................................................. 4-29
Chapter 5
Debug Support
5.1 Overview............................................................................................................. 5-1
5.2 Signal Description............................................................................................... 5-2
5.3 Real-Time Trace Support.................................................................................... 5-3
5.3.1 Begin Execution of Taken Branch (PST = 0x5)............................................. 5-4
5.4 Programming Model........................................................................................... 5-5
5.4.1 Address Attribute Trigger Register (AATR).................................................. 5-7
5.4.2 Address Breakpoint Registers (ABLR, ABHR) ............................................ 5-8
5.4.3 BDM Address Attribute Register (BAAR)..................................................... 5-9
5.4.4 Configuration/Status Register (CSR)............................................................ 5-10
5.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)......................................... 5-12
5.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)...................... 5-13
5.4.7 Trigger Definition Register (TDR)............................................................... 5-14
5.5 Background Debug Mode (BDM) .................................................................... 5-16
5.5.1 CPU Halt....................................................................................................... 5-16
5.5.2 BDM Serial Interface.................................................................................... 5-17
5.5.2.1 Receive Packet Format ............................................................................. 5-19
5.5.2.2 Transmit Packet Format............................................................................ 5-19
5.5.3 BDM Command Set...................................................................................... 5-19
5.5.3.1 ColdFire BDM Command Format............................................................ 5-20
5.5.3.1.1 Extension Words as Required............................................................... 5-21
5.5.3.2 Command Sequence Diagrams................................................................. 5-21
5.5.3.3 Command Set Descriptions ...................................................................... 5-23
5.5.3.3.1 Read A/D Register (
RAREG / RDREG ) ..................................................... 5-24
5.5.3.3.2 Write A/D Register (
WAREG / WDREG )................................................... 5-25
5.5.3.3.3 Read Memory Location (
READ )............................................................ 5-26
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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