Datasheet

Chapter 2. ColdFire Core 2-41

Instruction Timing

certain hardware resources within the processor are marked as “busy” for two clock

cycles after the ﬁnal DSOC cycle of the store instruction. If a subsequent store

instruction is encountered within this two-cycle window, it is stalled until the

resource again becomes available. Thus, the maximum pipeline stall involving

consecutive store operations is two cycles.

• The OEP can complete all memory accesses without memory causing any stall

conditions. Thus, timing details in this section assume an inﬁnite zero-wait state

memory attached to the core.

• All operand data accesses are assumed to be aligned on the same byte boundary as

the operand size:

— 16-bit operands aligned on 0-modulo-2 addresses

— 32-bit operands aligned on 0-modulo-4 addresses

Operands that do not meet these guidelines are misaligned. Table 2-9 shows how the

core decomposes a misaligned operand reference into a series of aligned accesses.

2.7.1 MOVE Instruction Execution Times

The execution times for the MOVE.{B,W,L} instructions are shown in the next tables.

Table 2-12 shows the timing for the other generic move operations.

NOTE:

For all tables in this chapter, the execution time of any

instruction using the PC-relative effective addressing modes is

equivalent to the time using comparable An-relative mode.

ET with {<ea> = (d16,PC)} equals ET with {<ea> = (d16,An)}

ET with {<ea> = (d8,PC,Xi*SF)} equals ET with {<ea> = (d8,An,Xi*SF)}

The nomenclature “(xxx).wl” refers to both forms of absolute

addressing, (xxx).w and (xxx).l.

Table 2-9. Misaligned Operand References

A[1:0] Size Bus Operations Additional C(R/W)

Each timing entry is presented as C(r/w), described as follows:

C is the number of processor clock cycles, including all applicable operand fetches and writes, as

well as all internal core cycles required to complete the instruction execution.

r/w is the number of operand reads (r) and writes (w) required by the instruction. An operation

performing a read-modify write function is denoted as (1/1).

x1 Word Byte, Byte 2(1/0) if read

1(0/1) if write

x1 Long Byte, Word, Byte 3(2/0) if read

2(0/2) if write

10 Long Word, Word 2(1/0) if read

1(0/1) if write

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