Datasheet

2-46 MCF5307 User’s Manual
Instruction Timing
2.7.5 Branch Instruction Execution Times
Table 2-16 shows general branch instruction timing.
For the conditional branch opcodes (bcc), a static algorithm is used to determine the
prediction state of the branch. This algorithm is:
if bcc is a forward branch && CCR[7] == 0
then the bcc is predicted as not-taken
nop 3(0/0) — — — — — — —
pea Í — 2(0/1) — — 2(0/1)
3
3(0/1)
4
2(0/1) —
pulse 1(0/0) — — — — — — —
stop #imm — — — — — — — 3(0/0)
5
trap #imm — — — — — — — 18(1/2)
trapf 1(0/0) — — — — — — —
trapf.w 1(0/0) — — — — — — —
trapf.l 1(0/0) — — — — — — —
unlk Ax 3(1/0) — — — — — — —
wddata.l Í — 7(1/0) 7(1/0) 7(1/0) 7(1/0) 8(1/0) 7(1/0) —
wdebug.l Í — 10(2/0) — — 10(2/0) — — —
1
If a MOVE.W #imm,SR instruction is executed and #imm[13] = 1, the execution time is 1(0/0).
2
n is the number of registers moved by the MOVEM opcode.
3
PEA execution times are the same for (d16,PC).
4
PEA execution times are the same for (d8,PC,Xi*SF).
5
The execution time for STOP is the time required until the processor begins sampling continuously for
interrupts.
Table 2-16. General Branch Instruction Execution Times
Opcode Í
Effective Address
Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
bra ————1(0/1)
1
1
Assumes branch acceleration. Depending on the pipeline status, execution times may vary from 1 to 3 cycles.
———
bsr — — — — 1(0/1)
1
———
jmp Í — 5(0/0) — — 5(0/0)
1
6(0/0) 1(0/0)
1
—
jsr Í — 5(0/1) — — 5(0/1) 6(0/1) 1(0/1)
1
—
rte — — 14(2/0) — — — — —
rts — — 8(1/0) — — — — —
Table 2-15. Miscellaneous Instruction Execution Times (Continued)
Opcode Í
Effective Address
Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
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