Datasheet

Chapter 2. ColdFire Core 2-47
Exception Processing Overview
if bcc is a forward branch && CCR[7] == 1
then the bcc is predicted as taken
else if bcc is a backward branch
then the bcc is predicted as taken
Table 2-17 shows timing for Bcc instructions.
2.8 Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. Differences
from previous M68000 Family processors include the following:
• A simplified exception vector table
• Reduced relocation capabilities using the vector base register
• A single exception stack frame format
• Use of a single, self-aligning system stack pointer
ColdFire processors use an instruction restart exception model but require more software
support to recover from certain access errors. See Table 2-18 for details.
Exception processing can be defined as the time from the detection of the fault condition
until the fetch of the first handler instruction has been initiated. It is comprised of the
following four major steps:
1. The processor makes an internal copy of the SR and then enters supervisor mode by
setting SR[S] and disabling trace mode by clearing SR[T]. The occurrence of an
interrupt exception also forces SR[M] to be cleared and the interrupt priority mask
to be set to the level of the current interrupt request.
2. The processor determines the exception vector number. For all faults except
interrupts, the processor performs this calculation based on the exception type. For
interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to
obtain the vector number from a peripheral device. The IACK cycle is mapped to a
special acknowledge address space with the interrupt level encoded in the address.
3. The processor saves the current context by creating an exception stack frame on the
system stack. ColdFire processors support a single stack pointer in the A7 address
register; therefore, there is no notion of separate supervisor and user stack pointers.
As a result, the exception stack frame is created at a 0-modulo-4 address on the top
of the current system stack. Additionally, the processor uses a simplified
Table 2-17. Bcc Instruction Execution Times
Opcode
Predicted
Correctly as Taken
Predicted
Correctly as Not
Taken
Predicted
Incorrectly
bcc 1(0/0) 1(0/0) 5(0/0)
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