Datasheet

2-48 MCF5307 User’s Manual
Exception Processing Overview
xed-length stack frame for all exceptions. The exception type determines whether
the program counter in the exception stack frame denes the address of the faulting
instruction (fault) or of the next instruction to be executed (next).
4. The processor acquires the address of the rst instruction of the exception handler.
The exception vector table is aligned on a 1-Mbyte boundary. This instruction
address is obtained by fetching a value from the table at the address dened in the
vector base register. The index into the exception table is calculated as
4 x vector_number. When the index value is generated, the vector table contents
determine the address of the rst instruction of the desired handler. After the fetch
of the rst opcode of the handler is initiated, exception processing terminates and
normal instruction processing continues in the handler.
ColdFire processors support a 1024-byte vector table aligned on any 1-Mbyte address
boundary; see Table 2-18. The table contains 256 exception vectors where the rst 64 are
dened by Motorola; the remaining 192 are user-dened interrupt vectors.
Table 2-18. Exception Vector Assignments
Vector Numbers Vector Offset (Hex) Stacked Program Counter
1
Assignment
0 000 Initial stack pointer
1 004 Initial program counter
2 008 Fault Access error
3 00C Fault Address error
4 010 Fault Illegal instruction
5 014 Fault Divide by zero
6–7 018–01C Reserved
8 020 Fault Privilege violation
9 024 Next Trace
10 028 Fault Unimplemented line-a opcode
11 02C Fault Unimplemented line-f opcode
12 030 Next Debug interrupt
13 034 Reserved
14 038 Fault Format error
15 03C Next Uninitialized interrupt
16–23 040–05C Reserved
24 060 Next Spurious interrupt
25–31 064–07C Next Level 1–7 autovectored interrupts
32–47 080–0BC Next Trap #0–15 instructions
48–60 0C0–0F0 Reserved
61 0F4 Fault Unsupported instruction
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