Datasheet

Chapter 2. ColdFire Core 2-49
Exception Processing Overview
ColdFire processors inhibit sampling for interrupts during the first instruction of all
exception handlers. This allows any handler to effectively disable interrupts, if necessary,
by raising the interrupt mask level contained in the status register.
2.8.1 Exception Stack Frame Definition
The exception stack frame is shown in Figure 2-10. The first longword of the exception
stack frame contains the 16-bit format/vector word (F/V) and the 16-bit status register. The
second longword contains the 32-bit program counter address.
The 16-bit format/vector word contains three unique fields:
• Format field—This 4-bit field at the top of the system stack is always written with a
value of {4,5,6,7} by the processor indicating a 2-longword frame format. See
Table 2-19. This field records any longword misalignment of the stack pointer that
may have existed when the exception occurred.
• Fault status field—The 4-bit field, FS[3–0], at the top of the system stack is defined
for access and address errors along with interrupted debug service routines. See
Table 2-20.
62–63 0F8–0FC — Reserved
64–255 100–3FC Next User-defined interrupts
1
The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC
of the instruction that immediately follows the instruction that caused the fault.
31 28 27 26 25 18 17 16 15 0
A7→ Format FS[3–2] Vector[7–0] FS[1–0] Status Register
+ 0x04 Program Counter [31–0]
Figure 2-10. Exception Stack Frame Form
Table 2-19. Format Field Encoding
Original A7 at Time of
Exception, Bits 1–0
A7 at First Instruction of
Handler
Format Field Bits
31–28
00 Original A[7–8] 0100
01 Original A[7–9] 0101
10 Original A[7–10] 0110
11 Original A[7–11] 0111
Table 2-18. Exception Vector Assignments (Continued)
Vector Numbers Vector Offset (Hex) Stacked Program Counter
1
Assignment
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...