Datasheet

Chapter 4. Local Memory 4-1
Chapter 4
Local Memory
This chapter describes the MCF5307 implementation of the ColdFire Version 3 local
memory specification. It consists of two major sections.
• Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM
(SRAM) implementation. It covers general operations, configuration, and
initialization. It also provides information and examples showing how to minimize
power consumption when using the SRAM.
• Section 4.7, “Cache Overview,” describes the MCF5307 cache implementation,
including organization, configuration, and coherency. It describes cache operations
and how the cache interfaces with other memory structures.
4.1 Interactions between Local Memory Modules
Depending on configuration information, instruction fetches and data read accesses may be
sent simultaneously to the RAM and cache controllers. This approach is required because
both controllers are memory-mapped devices and the hit/miss determination is made
concurrently with the read data access. Power dissipation can be minimized by configuring
the RAMBARs to mask unused address spaces whenever possible.
If the access address is mapped into the region defined by the RAM (and this region is not
masked), the RAM provides the data back to the processor, and the cache data is discarded.
Accesses from the RAM module are never cached. The complete definition of the
processor’s local bus priority scheme for read references is as follows:
if (RAM “hits”
) RAM supplies data to the processor
else if (cache “hits”)
cache supplies data to the processor
else system memory reference to access data
For data write references, the memory mapping into the local memories is resolved before
the appropriate destination memory is accessed. Accordingly, only the targeted local
memory is accessed for data write transfers.
4.2 SRAM Overview
The 4-Kbyte on-chip SRAM module is connected to the internal bus and provides pipelined,
single-cycle access to memory mapped to the module. Memory can be mapped to any
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