MCF5407 ColdFire® Integrated Microprocessor User’s Manual MCF5407UM/D Rev. 0.
ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductors Motorola reserves the right to make changes without further notice to any products herein.
Overview Part I: MCF5407 Processor Core 1 Part I ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 Part II: System Integration Module (SIM) Part II SIM Overview 6 Phase-Locked Loop (PLL) 7 I2C Module 8 Interrupt Controller 9 Chip-Select Module 10 Synchronous/Asynchronous DRAM Controller Module 11 Part III: Peripheral Module Part III DMA Controller Module 12 Timer Module 13 UART Modules 14 Parallel Port (General-Purpose I/O) 15 Part IV
1 Part I Overview Part I: MCF5407 Processor Core 2 ColdFire Core 3 Hardware Multiply/Accumulate (MAC) Unit 4 Local Memory 5 Debug Support Part II Part II: System Integration Module (SIM) 6 SIM Overview 7 Phase-Locked Loop (PLL) 8 I2C Module 9 Interrupt Controller 10 Chip-Select Module 11 Synchronous/Asynchronous DRAM Controller Module Part III Part III: Peripheral Module 12 DMA Controller Module 13 Timer Module 14 UART Modules 15 Parallel Port (General-Purpose I/O) Part IV
CONTENTS Paragraph Number Title Page Number Chapter 1 Overview 1.1 1.2 1.2.1 1.3 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.2 1.3.2.1 1.3.2.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 1.3.8.1 1.3.8.2 1.3.8.3 1.3.8.4 1.3.8.5 1.3.9 1.3.10 1.4 1.4.1 1.4.2 Features ............................................................................................................... 1-1 MCF5407 Features.............................................................................................. 1-4 Process ..............
CONTENTS Paragraph Number 1.4.3 1.4.4 Title Page Number Supervisor Registers ..................................................................................... 1-16 Instruction Set ............................................................................................... 1-16 Part I MCF5407 Processor Core Chapter 2 ColdFire Core 2.1 2.1.1 2.1.2 2.1.2.1 2.1.2.1.1 2.1.2.2 2.1.2.2.1 2.1.2.2.2 2.1.2.2.3 2.1.2.3 2.1.3 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 2.2.1.4 2.2.1.5 2.2.1.6 2.2.2 2.2.2.1 2.2.2.2 2.
CONTENTS Paragraph Number 2.6.2 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.8 2.8.1 2.8.2 2.9 Title Page Number Instruction Set Summary .............................................................................. Execution Timings ............................................................................................ MOVE Instruction Execution Timing .......................................................... Execution Timings—One-Operand Instructions ..........................................
CONTENTS Paragraph Number 4.9.2 4.9.3 4.9.3.1 4.9.3.2 4.9.3.3 4.9.3.4 4.9.4 4.9.5 4.9.5.1 4.9.5.2 4.9.5.2.1 4.9.5.2.2 4.9.6 4.10 4.10.1 4.10.2 4.11 4.12 4.12.1 4.12.2 4.13 Title Page Number Cache-Inhibited Accesses ............................................................................. Cache Protocol.............................................................................................. Read Miss .................................................................................................
CONTENTS Paragraph Number 5.4.9 5.5 5.5.1 5.5.2 5.5.2.1 5.5.2.2 5.5.3 5.5.3.1 5.5.3.1.1 5.5.3.2 5.5.3.3 5.5.3.3.1 5.5.3.3.2 5.5.3.3.3 5.5.3.3.4 5.5.3.3.5 5.5.3.3.6 5.5.3.3.7 5.5.3.3.8 5.5.3.3.9 5.5.3.3.10 5.5.3.3.11 5.5.3.3.12 5.5.3.3.13 5.6 5.6.1 5.6.1.1 5.6.2 5.7 5.8 5.8.1 5.8.2 Title Page Number Resulting Set of Possible Trigger Combinations.......................................... Background Debug Mode (BDM) .................................................................... CPU Halt...............
CONTENTS Paragraph Number 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.10.1 6.2.10.1.1 6.2.10.1.2 Title Page Number Module Base Address Register (MBAR) ....................................................... 6-4 Reset Status Register (RSR) ........................................................................... 6-5 Software Watchdog Timer.............................................................................. 6-6 System Protection Control Register (SYPCR) ..........................
CONTENTS Paragraph Number 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 Title Page Number I2C Address Register (IADR) ......................................................................... 8-6 I2C Frequency Divider Register (IFDR)......................................................... 8-6 I2C Control Register (I2CR) ........................................................................... 8-7 I2C Status Register (I2SR)..................................................
CONTENTS Paragraph Number 11.1 11.1.1 11.1.2 11.2 11.2.1 11.3 11.3.1 11.3.2 11.3.2.1 11.3.2.2 11.3.2.3 11.3.3 11.3.3.1 11.3.3.2 11.3.3.3 11.3.3.4 11.3.3.5 11.4 11.4.1 11.4.2 11.4.3 11.4.3.1 11.4.3.2 11.4.3.3 11.4.4 11.4.4.1 11.4.4.2 11.4.4.3 11.4.4.4 11.4.4.5 11.4.4.6 11.4.5 11.4.5.1 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 xii Title Page Number Overview........................................................................................................... 11-1 Definitions .....................
CONTENTS Paragraph Number Title Page Number Part III Peripheral Module Chapter 12 DMA Controller Module 12.1 12.1.1 12.2 12.3 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.4.6 12.5 12.5.1 12.5.2 12.5.2.1 12.5.2.2 12.5.3 12.5.3.1 12.5.3.2 12.5.4 12.5.4.1 12.5.4.2 12.5.4.3 12.5.5 Overview........................................................................................................... 12-1 DMA Module Features .................................................................................
CONTENTS Paragraph Number 13.3.5 13.4 13.5 Title Page Number Timer Event Registers (TER0/TER1)........................................................... 13-5 Code Example................................................................................................... 13-6 Calculating Time-Out Values ........................................................................... 13-7 Chapter 14 UART Modules 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 14.3.8 14.3.9 14.3.10 14.3.11 14.3.
CONTENTS Paragraph Number 14.5.2.4.1 14.5.2.5 14.5.2.6 14.5.3 14.5.3.1 14.5.3.2 14.5.3.3 14.5.4 14.5.5 14.5.5.1 14.5.5.2 14.5.5.3 14.5.6 14.5.6.1 Title Page Number Receiver in Modem Mode (UART1).................................................. FIFO Stack in UART0............................................................................ FIFOs in UART1 .................................................................................... Looping Modes ......................................................
CONTENTS Paragraph Number 17.2.1.1 17.2.1.2 17.2.2 17.2.3 17.2.4 17.2.5 17.2.6 17.2.7 17.2.8 17.2.9 17.2.10 17.3 17.3.1 17.4 17.4.1 17.4.2 17.4.3 17.5 17.5.1 17.5.2 17.5.3 17.5.4 17.5.5 17.5.5.1 17.5.5.2 17.5.5.3 17.5.5.4 17.5.6 17.5.6.1 17.6 17.6.1 17.6.2 17.6.3 17.7 17.7.1 17.7.2 17.7.3 17.7.4 17.7.5 17.7.6 17.7.7 17.8 17.8.1 xvi Title Page Number Address Bus (A[23:0]).............................................................................. 17-7 Address Bus (A[31:24]/PP[15:8]) ....................
CONTENTS Paragraph Number 17.8.2 17.9 17.9.1 17.9.2 17.9.3 17.9.4 17.10 17.10.1 17.10.2 17.11 17.12 17.12.1 17.12.2 17.13 17.13.1 17.13.2 17.13.3 17.13.4 17.14 17.14.1 17.14.2 17.14.3 17.14.4 17.14.5 Title Page Number Transfer Modifier/DMA Acknowledge (TM[2:0]/DACK[1:0]) ................ Serial Module Signals ..................................................................................... Transmitter Serial Data Output (TxD)........................................................
CONTENTS Paragraph Number 18.4.7.4 18.5 18.6 18.7 18.7.1 18.7.2 18.8 18.8.1 18.9 18.9.1 18.9.2 18.10 18.10.1 18.10.2 Title Page Number Transfers Using Mixed Port Sizes .......................................................... Misaligned Operands ...................................................................................... Bus Errors ....................................................................................................... Interrupt Exceptions........................................
CONTENTS Paragraph Number 20.9 20.10 20.11 Title Page Number Parallel Port (General-Purpose I/O) Timing Specifications ........................... 20-22 DMA Timing Specifications........................................................................... 20-23 IEEE 1149.1 (JTAG) AC Timing Specifications ........................................... 20-24 Appendix A Migrating from the ColdFire MCF5307 to the MCF5407 A.1 A.2 A.3 A.4 A.5 A.6 A.6.1 A.6.2 A.7 A.8 A.8.1 A.8.2 A.8.2.1 A.8.3 A.8.3.1 A.8.3.2 A.8.3.
CONTENTS Paragraph Number xx Title MCF5407 User’s Manual Page Number
ILLUSTRATIONS Figure Number 1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-1 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 5-1 5-2 5-3 5-4 5-5 5-6 Title Page Number MCF5407 Block Diagram............................................................................................. 1-2 UART Module Block Diagram................................................................................... 1-10 PLL Module .....................................................................
ILLUSTRATIONS Figure Page Title Number Number 5-7 Address Breakpoint Registers (ABLR, ABHR, ABLR1, ABHR1)............................ 5-12 5-8 BDM Address Attribute Register (BAAR)................................................................. 5-13 5-9 Configuration/Status Register (CSR).......................................................................... 5-13 5-10 Data Breakpoint/Mask Registers (DBR/DBR1 and DBMR/DBMR1).......................
ILLUSTRATIONS Figure Number 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 7-1 7-2 7-3 7-4 7-5 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 Title Page Number MCF5407 Embedded System Recovery from Unterminated Access........................... 6-7 System Protection Control Register (SYPCR) ............................................................ 6-8 Software Watchdog Interrupt Vector Register (SWIVR).........................
ILLUSTRATIONS Figure Page Title Number Number 11-10 Write Hit in Continuous Page Mode......................................................................... 11-15 11-11 EDO Read Operation (3-2-2-2) ................................................................................ 11-15 11-12 DRAM Access Delayed by Refresh ......................................................................... 11-16 11-13 MCF5407 SDRAM Interface...............................................................................
ILLUSTRATIONS Figure Number 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 14-24 14-23 14-25 14-26 14-27 14-28 14-29 14-30 14-31 14-32 14-33 14-34 14-35 14-36 14-37 14-38 14-39 15-1 15-2 15-3 16-1 16-2 16-3 17-1 17-2 Title Page Number Modem Control Register (MODCTL) ........................................................................ 14-9 Tx FIFO Threshold Register (TXLVL) ....................................................................
ILLUSTRATIONS Figure Page Title Number Number 18-1 Signal Relationship to CLKIN for Non-DRAM Access............................................. 18-2 18-2 Connections for External Memory Port Sizes ............................................................ 18-4 18-3 Chip-Select Module Output Timing Diagram ............................................................ 18-4 18-4 Data Transfer State Transition Diagram .....................................................................
ILLUSTRATIONS Figure Number 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 20-17 20-18 20-19 20-20 20-21 20-22 20-23 20-24 A-1 A-2 A-3 A-4 A-5 A-6 A-7 Title Page Number PSTCLK Timing......................................................................................................... 20-6 AC Timings—Normal Read and Write Bus Cycles ................................................... 20-8 SDRAM Read Cycle with EDGESEL Tied to Buffered CLKIN ...............................
ILLUSTRATIONS Figure Number xxviii Title MCF5407 User’s Manual Page Number
9/1/00 TABLES Table Number 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 Title Page Number User-Level Registers................................................................................................... 1-15 Supervisor-Level Registers......................................................................................... 1-16 CCR Field Descriptions ....................................
TABLES Table Number 4-10 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 xxx Title Page Number Data Cache Line State Transitions (Current State Modified)..................................... 4-31 Debug Module Signals..................................................................................................
TABLES Table Number 8-5 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 Title Page Number I2SR Field Descriptions................................................................................................ 8-9 Interrupt Controller Registers .......................................................................................
TABLES Table Number 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 11-36 11-37 12-1 12-2 12-3 12-4 12-5 13-1 13-2 13-3 13-4 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 15-1 15-2 xxxii Title Page Number MCF5407 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) ............. 11-26 MCF5407 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)................
TABLES Table Number 15-3 16-1 16-2 16-3 16-4 16-5 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 19-1 19-2 19-3 19-4 20-1 20-2 20-3 20-4 20-5 20-6 Title Page Number Relationship between PADAT Register and Parallel Port Pin (PP) ........................... 15-3 Pins 1–52 (Left, Top-to-Bottom) ................................................................................
TABLES Table Number 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9 B-10 xxxiv Title Page Number Output AC Timing Specification ................................................................................ 20-6 Reset Timing Specification....................................................................................... 20-15 Debug AC Timing Specification ...........................................
About This Book The primary objective of this user’s manual is to define the functionality of the MCF5407 processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are using the most recent version of the documentation.
Organization — Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the MCF5407 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). • — Chapter 4, “Local Memory.” This chapter describes the MCF5407 implementation of the ColdFire V4 local memory specification. It consists of the two following major sections. – Section 4.
Organization controller component of the SIM. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. • • Part III, “Peripheral Module,” describes the operation and configuration of the MCF5407 DMA, timer, UART, and parallel port modules, and describes how they interface with the system integration unit, described in Part II.
Suggested Reading — Chapter 20, “Electrical Specifications,” describes AC and DC electrical specifications and thermal characteristics for the MCF5407. Because additional speeds may have become available since the publication of this book, consult Motorola’s ColdFire web page, http://www.motorola.com/coldfire, to confirm that this is the latest information.
Conventions • Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire documentation, refer to the World Wide Web at http://www.motorola.com/ColdFire/. Conventions This document uses the following notational conventions: MNEMONICS In text, instruction mnemonics are shown in uppercase.
Acronyms and Abbreviations Table i.
Terminology and Notational Conventions Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning POR Power-on reset PQFP Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Terminology and Notational Conventions Table ii shows notational conventions used throughout this document.
Terminology and Notational Conventions Table ii Notational Conventions (Continued) Instruction Operand Syntax Register Names ACC MAC accumulator register CCR Condition code register (lower byte of SR) MACSR MAC status register MASK MAC mask register PC Program counter SR Status register Port Name PSTDDATA Processor status/debug data port Miscellaneous Operands # y,x
Terminology and Notational Conventions Table ii Notational Conventions (Continued) Instruction Operand Syntax / Arithmetic division ~ Invert; operand is logically complemented & Logical AND | Logical OR ^ Logical exclusive OR << Shift left (example: D0 << 3 is shift D0 left 3 bits) >> Shift right (example: D0 >> 3 is shift D0 right 3 bits) → Source operand is moved to destination operand ←→ Two operands are exchanged sign-extended All bits of the upper portion are made equal to the hig
Terminology and Notational Conventions xliv MCF5407 User’s Manual
Chapter 1 Overview This chapter is an overview of the MCF5407 ColdFire® processor. It includes general descriptions of the modules and features incorporated in the MCF5407, focusing in particular on new features defined by the Version 4 (V4) programming model, such as the Harvard memory architecture implementation, new instructions, and new registers. 1.
Features V4 COLDFIRE PROCESSOR COMPLEX Instruction Unit 8-Entry Branch Cache .. .
Features Features common to many embedded applications, such as DMAs, various DRAM controller interfaces, and on-chip memories, are integrated using advanced process technologies. The MCF5407 extends the legacy of Motorola’s 68K family by providing a compatible path for 68K and ColdFire customers in which development tools and customer code can be leveraged.
MCF5407 Features 1.
MCF5407 Features • • • • • Two, 2-Kbyte SRAMs — Programmable location anywhere within 4-Gbyte linear address space — Higher core-frequency operation — Pipelined, single-cycle access to critical code or data — Each block mappable to either the instruction or data operand bus DMA controller — Four fully programmable channels: two support external requests and external acknowledges — Dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability — Source/destination address poi
MCF5407 Features • • • • • • • 1-6 I2C module — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I2C bus — Master or slave modes support multiple masters — Automatic interrupt generation with programmable level System interface module (SIM) — Chip selects provide direct interface to 8-, 16-, and 32-bit SRAM, ROM, FLASH, and memory-mapped I/O devices — Eight fully programmable chip selects, each with a base address register — P
ColdFire Module Description 1.2.1 Process The MCF5407 is manufactured in a 0.22-µ CMOS process with quad-layer-metal routing technology. This process combines the high performance and low power needed for embedded system applications. Inputs are 3.3-V tolerant; outputs are CMOS or open-drain CMOS with outputs operating from VDD + 0.5 V to GND - 0.5 V, with guaranteed TTL-level specifications. 1.
ColdFire Module Description 1.3.1.2 Operand Execution Pipeline (OEP) The prefetched instruction stream is gated from the FIFO buffer into the five-stage OEP. The OEP consists of two, traditional two-stage RISC compute engines with a register file access feeding an arithmetic/logic unit (ALU).
ColdFire Module Description 1.3.2.1 16-Kbyte Instruction Cache/8-Kbyte Data Cache The MCF5407 Harvard architecture includes a 16-Kbyte instruction cache and an 8-Kbyte data cache. These four-way, set-associative caches provide pipelined, single-cycle access on cached instructions and operands. As with all ColdFire caches, the cache controllers implement a non-lockup, streaming design.
ColdFire Module Description 1.3.5 UART Modules The MCF5407 contains two UARTs, which function independently. One UART has been enhanced to provide synchronous operation and a CODEC interface for soft modem support. Either UART can be clocked by the system bus clock, eliminating the need for an external crystal. Each UART module interfaces directly to the CPU, as shown in Figure 1-2.
ColdFire Module Description and remote loopback modes allow testing of UART connections. The programmable UARTs can interrupt the CPU on various normal or error-condition events. 1.3.6 Timer Module The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer for use in any of three modes. One mode captures the timer value with an external event.
ColdFire Module Description or 32-bit ports. The base address, access permissions, and internal bus transfer terminations are programmable with configuration registers for each chip select. CS0 also provides global chip select functionality of boot ROM upon reset for initializing the MCF5407. 1.3.8.3 16-Bit Parallel Port Interface A 16-bit general-purpose programmable parallel port serves as either an input or an output on a pin-by-pin basis. 1.3.8.
Programming Model, Addressing Modes, and Instruction Set To support program trace, the Version 4 debug module has combined the processor status and debug data outputs into a single 8-bit bus (PSTDDATA[7:0]). This bus and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at one-half the CPU’s clock rate. 1.3.10 PLL Module The MCF5407 PLL module is shown in Figure 1-3.
Programming Model, Addressing Modes, and Instruction Set • • 1-14 User mode—When the processor is in user mode (SR[S] = 0), only a subset of registers can be accessed, and privileged instructions cannot be executed. Typically, most application processing occurs in user mode. User mode is usually entered by executing a return from exception instruction (RTE, assuming the value of SR[S] saved on the stack is 0) or a MOVE, SR instruction (assuming SR[S] is 0).
Programming Model, Addressing Modes, and Instruction Set 1.4.1 Programming Model Figure 1-4 shows the MCF5407 programming model.
Programming Model, Addressing Modes, and Instruction Set Table 1-1. User-Level Registers (Continued) Register Description Program counter (PC) Contains the address of the instruction currently being executed by the MCF5407 processor Condition code register (CCR) The CCR is the lower byte of the SR. It contains indicator flags that reflect the result of a previous operation and are used for conditional instruction execution.
Programming Model, Addressing Modes, and Instruction Set operation sizes, and assembler syntax. For two-operand instructions, the first operand is generally the source operand and the second is the destination. Because the ColdFire architecture provides an upgrade path for 68K customers, its instruction set supports most of the common 68K opcodes. A majority of the instructions are binary compatible or optimized 68K opcodes.
Programming Model, Addressing Modes, and Instruction Set 1-18 MCF5407 User’s Manual
Part I MCF5407 Processor Core Intended Audience Part I is intended for system designers who need a general understanding of the functionality supported by the MCF5407. It also describes the operation of the MCF5407 ColdFire core and its multiply/accumulate (MAC) execution unit. It describes the programming and exception models, Harvard memory implementation, and debug module. Contents • • • Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the MCF5407.
• Chapter 5, “Debug Support,” describes the Revision C enhanced hardware debug support in the MCF5407. This revision of the ColdFire debug architecture encompasses earlier revisions. Suggested Reading The following literature may be helpful with respect to the topics in Part I: • • ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D.
Table I-i.
I-xxii MCF5407 User’s Manual
Chapter 2 ColdFire Core This chapter provides an overview of the microprocessor core of the MCF5407. The chapter begins with a description of enhancements from the Version 3 (V3) ColdFire core, and then fully describes the V4 programming model as it is implemented on the MCF5407. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. 2.
Features and Enhancements • • Vector base register to relocate exception-vector table Optimized for high-level language constructs 2.1.1 Clock-Multiplied Microprocessor Core The MCF5407 incorporates a clock-multiplying phase-locked loop (PLL). Increasing the internal speed of the core also allows higher performance while providing the system designer with an easy-to-use lower speed system interface. The frequency of the processor complex is an integer multiple of the external bus speed.
Features and Enhancements — Write data available (DA) makes data available for operand write operations only. — Store data (ST) updates memory element for operand write operations only. Instruction Fetch Pipeline IAG Branch Cache Instruction Memory IC1 IC2 Branch Accel. IED IB Internal Bus Operand Execution Pipeline DS secDS OAG Data (Operand) Memory OC1 OC2 Misalignment Module EX DA Debug DSCLK DSI DSO DDATA PSTDDATA PSTCLK Figure 2-1. ColdFire Enhanced Pipeline Chapter 2.
Features and Enhancements 2.1.2.1 Instruction Fetch Pipeline (IFP) Because the fetch and execution pipelines are decoupled by a ten-instruction FIFO buffer, the IFP can prefetch instructions before the OEP needs them, minimizing stalls. 2.1.2.1.1 Branch Acceleration To maximize the performance of conditional branch instructions, the IFP implements a sophisticated two-level acceleration mechanism.
Features and Enhancements • Instruction folding involving MOVE instructions allows two instructions to be issued in one cycle. The resulting microarchitecture approaches full superscalar performance at a much lower silicon cost. 2.1.2.2.1 Illegal Opcode Handling To aid in conversion from M68000 code, every 16-bit operation word is decoded to ensure that each instruction is valid.
Features and Enhancements 2.1.2.2.3 Hardware Divide Unit The hardware divide unit performs the following integer division operations: • • • 32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder 32-bit operand/32-bit operand producing a 32-bit quotient 32-bit operand/32-bit operand producing a 32-bit remainder 2.1.2.
Programming Model These registers can be accessed through the dedicated debug serial communication channel, or from the processor’s supervisor programming model, using the WDEBUG instruction. The MCF5407’s new interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging.
Programming Model 31 0 Data registers A0 A1 A2 A3 A4 A5 A6 A7 PC CCR Address registers MACSR ACC MASK MAC status register MAC accumulator MAC mask register SR VBR CACR ACR0 ACR1 ACR2 ACR3 RAMBAR0 RAMBAR1 MBAR Status register Vector base register Cache control register Access control register 0 (data) Access control register 1 (data) Access control register 2 (instruction) Access control register 3 (instruction) RAM 0 base address register RAM 1 base address register Module base address register 0
Programming Model 2.2.1.2 Address Registers (A0–A6) The address registers (A0–A6) can be used as software stack pointers, index registers, or base address registers and may be used for word and longword operations. 2.2.1.3 Stack Pointer (A7, SP) The processor core supports a single hardware stack pointer (A7) used during stacking for subroutine calls, returns, and exception handling.
Programming Model Table 2-1. CCR Field Descriptions Bits Name Description 7–5 — Reserved, should be cleared. 4 X Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not affected or set to a specified result. Also used as an input operand for multiple-precision arithmetic. 3 N Negative condition code bit. Set if the msb of the result is set; otherwise cleared. 2 Z Zero condition code bit. Set if the result equals zero; otherwise cleared.
Programming Model Table 2-2. MOVEC Register Map Rc[11–0] Register Definition 0x002 Cache control register (CACR) 0x004 Access control register 0 (ACR0) 0x005 Access control register 1 (ACR1) 0x006 Access control register 2 (ACR2) 0x007 Access control register 3 (ACR3) 0x801 Vector base register (VBR) 0xC04 RAM base address register 0 (RAMBAR0) 0xC05 RAM base address register 1 (RAMBAR1) 0xC0F Module base address register (MBAR) 2.2.2.
Programming Model 2.2.2.2 Vector Base Register (VBR) The VBR holds the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. VBR[19–0] are not implemented and are assumed to be zero, forcing the vector table to be aligned on a 0-modulo-1-Mbyte boundary.
Integer Data Formats 2.3 Integer Data Formats Table 2-4 lists the integer operand data formats. Integer operands can reside in registers, memory, or instructions. The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. Table 2-4. Integer Data Formats Operand Data Format Size Bit 1 bit Byte integer 8 bits Word integer 16 bits Longword integer 32 bits 2.
Organization of Data in Registers operands are sign-extended to 32 bits and then used in the operation with anaddress register destination. When an address register is a destination, the entire register is affected, regardless of the operation size. Figure 2-8 shows integer formats for address registers. 31 16 15 0 Sign-Extended 16-Bit Address Operand 31 0 Full 32-Bit Address Operand Figure 2-8.
Addressing Mode Summary 2.5 Addressing Mode Summary Addressing modes are categorized by how they are used. Data addressing modes refer to data operands. Memory addressing modes refer to memory operands. Alterable addressing modes refer to alterable (writable) data operands. Control addressing modes refer to memory operands without an associated size. These categories sometimes combine to form more restrictive categories.
Instruction Set Summary Table 2-6.
Instruction Set Summary Table 2-6.
Instruction Set Summary Table 2-6. Notational Conventions (Continued) Instruction Operand Syntax Condition Code Register Bit Names C Carry N Negative V Overflow X Extend Z Zero 2.6.1 Additions to the Instruction Set Architecture The original ColdFire instruction set architecture (ISA) was derived from the M68000 Family opcodes based on extensive analysis of embedded application code.
Instruction Set Summary • Enhancements to existing Revision_A instructions: — Longword support for branch instructions (Bcc, BRA, BSR) — Byte and word support for compare instructions (CMP, CMPI) — Word support for the compare address register instruction (CMPA) — Byte and longword support for MOVE.x ,where the source is immediate data and the destination is specified by d16(Ax); that is, MOVE.
Instruction Set Summary Table 2-8. User-Level Instruction Set Summary (Continued) Instruction Operand Syntax Operand Size Operation ADDI #,Dx .L Immediate data + destination → destination ADDQ #,x .L Immediate data + destination → destination ADDX Dy,Dx .L Source + destination + X → destination AND Dy,x y,Dx .L .L Source & destination → destination ANDI #,Dx .L Immediate data & destination → destination ASL Dy,Dx #,Dx .L .
Instruction Set Summary Table 2-8. User-Level Instruction Set Summary (Continued) Instruction Operand Syntax Operand Size Operation LINK Ax,# .W SP – 4 → SP; Ax → (SP); SP → Ax; SP + d16 → SP LSL Dy,Dx #,Dx .L .L X/C ← (Dx << Dy) ← 0 X/C ← (Dx << #) ← 0 LSR Dy,Dx #,Dx .L .L 0 → (Dx >> Dy) → X/C 0 → (Dx >> #) → X/C MAC Ry,RxSF .L + (.W × .W) → .L .L + (.L × .L) → .
Instruction Set Summary Table 2-8. User-Level Instruction Set Summary (Continued) Instruction Operand Syntax Operand Size Operation NOP none Unsized Synchronize pipelines; PC + 2 → PC NOT Dx .L ~ Destination → destination OR y,Dx Dy,x .L Source | destination → destination ORI #,Dx .L Immediate data | destination → destination PEA y .L SP – 4 → SP; Address of → (SP) PULSE none Unsized Set PST= 0x4 REMS ,Dx .
Execution Timings Table 2-9. Supervisor-Level Instruction Set Summary Instruction CPUSHL Operand Syntax Operand Size (An) Unsized Operation Invalidate instruction cache line Push and invalidate data cache line Push data cache line and invalidate (I,D)-cache lines HALT1 none Unsized Enter halted state INTOUCH (Ay) Unsized Touch instruction space at address Ay MOVE from SR SR, Dx .W SR → Dx MOVE to SR Dy,SR .W Source → SR #,SR MOVEC Ry,Rc .
Execution Timings In this sequence, the second instruction is held for three cycles stalling for the multiply instruction to update d0. If consecutive instructions update a register and use that register as a base of index value with a scale factor of 1 (Xi.l*1) in an address calculation, a two-cycle pipeline stall occurs. Using the destination register as an index register with any other scale factor (Xi.l*2, Xi.l*4) causes a three-cycle stall.
Execution Timings 2.7.1 MOVE Instruction Execution Timing Execution timing for the MOVE.{B,W,L} instructions are shown in the next tables. Table 2-13 shows the timing for the other generic move operations. NOTE: For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is equivalent to the time using comparable An-relative mode.
Execution Timings Table 2-12. Move Long Execution Times (Continued) Destination Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl -(Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (d16,Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — — (d8,Ay,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) — — — (xxx).w 1(1/0) 2(1/1) 2(1/1) 2(1/1) — — — — (xxx).
Execution Timings Table 2-14. One-Operand Instruction Execution Times Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #xxx clr.b 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — clr.w 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — clr.l 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — ext.w Dx 1(0/0) — — — — — — — ext.l Dx 1(0/0) — — — — — — — extb.l Dx 1(0/0) — — — — — — — neg.
Execution Timings Table 2-15. Two-Operand Instruction Execution Times (Continued) Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).
Execution Timings Table 2-15. Two-Operand Instruction Execution Times (Continued) Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # or.l Dy, — 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) — or.l #imm,Dx 1(0/0) — — — — — — — rems.l ,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) — — — remu.l ,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) — — — sub.
Execution Timings Table 2-16. Miscellaneous Instruction Execution Times (Continued) Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # unlk Ax 1(1/0) — — — — — — — wddata. {b,w,l} — 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) — wdebug.
Exception Processing Overview 2.8 Exception Processing Overview Exception processing for ColdFire processors is streamlined for performance.
Exception Processing Overview defined by Motorola; the remaining 192 are user-defined interrupt vectors. Table 2-19.
Exception Processing Overview 31 A7→ 28 Format 27 26 25 FS[3–2] + 0x04 18 Vector[7–0] 17 16 15 0 FS[1–0] Status Register Program Counter [31–0] Figure 2-1. Exception Stack Frame Form The 16-bit format/vector word contains three unique fields: • Format field—This 4-bit field at the top of the system stack is always written with a value of {4,5,6,7} by the processor indicating a 2-longword frame format. See Table 2-20.
Exception Processing Overview 2.8.2 Processor Exceptions Table 2-22 describes MCF5407 exceptions. Table 2-22. MCF5407 Exceptions Exception Description Access Error Access errors are reported only in conjunction with an attempted store to write-protected memory. Thus, access errors associated with instruction fetch or operand read accesses are not possible.
Exception Processing Overview Table 2-22. MCF5407 Exceptions (Continued) Exception Description Debug Interrupt Caused by a hardware breakpoint register trigger. Rather than generating an IACK cycle, the processor internally calculates the vector number (12 or 13, depending on the type of breakpoint trigger). Additionally, the M bit and the interrupt priority mask fields of the SR are unaffected by the interrupt. See Section 2.2.2.1, “Status Register (SR).
ColdFire Instruction Set Architecture Enhancements 2.9 ColdFire Instruction Set Architecture Enhancements This section describes the new opcodes implemented as part of the Revision B enhancements to the basic ColdFire ISA. In some cases, the opcodes represent minor enhancements to existing ColdFire functions, while in other cases, the functionality is new and not covered in the existing ISA.
ColdFire Instruction Set Architecture Enhancements Bcc Bcc Branch Conditionally If Condition True Then PC + dn → PC Operation: Assembler Syntax: Bcc
ColdFire Instruction Set Architecture Enhancements BRA BRA Branch Always Operation: PC + dn → PC Assembler Syntax: BRA
ColdFire Instruction Set Architecture Enhancements BSR BSR Branch to Subroutine Operation: SP – 4 → SP; PC → (SP); PC + dn → PC Assembler Syntax: BSR
ColdFire Instruction Set Architecture Enhancements CMP CMP Compare Operation: Destination – Source → cc Assembler Syntax: CMP y, Dx Attributes: Size = byte, word, long Description: Subtracts the source operand from the destination operand in the data register and sets condition codes according to the result; the data register is unchanged. The operation size may be a byte, word, or longword. CMPA is used when the destination is an address register; CMPI is used when the source is immediate data.
ColdFire Instruction Set Architecture Enhancements CMPA CMPA Compare Address Operation: Destination – Source → cc Assembler Syntax: CMPA y, Ax Attributes: Size = word, long Description: Operates similarly to CMP, but is used when the destination register is an address register rather than a data register. The operation size can be word or longword. Word-length source operands are sign-extended to 32 bits for comparison.
ColdFire Instruction Set Architecture Enhancements CMPI CMPI Compare Immediate Operation: Destination – Immediate Data → cc Assembler Syntax: CMPI #, Dx Attributes: Size = byte, word, long Description: Operates similarly to CMP, but is used when the source operand is immediate data. The size of the operation may be specified as byte, word, or longword. The size of the immediate data matches the operation size.
ColdFire Instruction Set Architecture Enhancements INTOUCH INTOUCH Instruction Fetch Touch Operation: If Supervisor State then Instruction Fetch Touch @ else TRAP Assembler Syntax INTOUCH Attributes: Unsized Description: Generates an instruction fetch reference at address (Ay). If the referenced address space is a cacheable region, this instruction can be used to prefetch a 16-byte packet into the processor’s instruction cache.
ColdFire Instruction Set Architecture Enhancements MOVE MOVE Move Data from Source to Destination Operation: Source → Destination Assembler Syntax: MOVE y, x Attributes: Size = byte, word, long Description: Moves the data at the source to the destination location and sets the condition codes according to the data. The size of the operation may be specified as byte, word, or longword.
ColdFire Instruction Set Architecture Enhancements Addressing Mode Mode Register Addressing Mode Mode Register Dy Ay (Ay) (Ay) + – (Ay) (d16,Ay) 000 001 010 011 100 101 reg. number:Dy reg. number:Ay reg. number:Ay reg. number:Ay reg. number:Ay reg. number:Ay (d8,Ay,Xi) (xxx).W (xxx).L # (d16,PC) (d8,PC,Xi) 110 111 111 111 111 111 reg. number:Ay 000 001 100 010 011 NOTE: Most assemblers use MOVEA when the destination is an address register.
ColdFire Instruction Set Architecture Enhancements MOVEA MOVEA Move Address from Source to Destination Operation: Source → Destination Assembler Syntax: MOVEA y, Ax Attributes: Size = word, long Description: Moves the address at the source to the destination location and sets the condition codes according to the data. The size of the operation may be specified as word or longword.
ColdFire Instruction Set Architecture Enhancements MOV3Q MOV3Q Move 3-Bit Data Quick Operation: Immediate Data → Destination Assembler Syntax MOV3Q #,x Attributes: Size = long Description: Move the immediate data to the operand at the destination location. The data range is from -1 to 7, excluding 0. The immediate data is zero-filled to a long operand and all 32 bits are transferred to the destination location.
ColdFire Instruction Set Architecture Enhancements MVS MVS Move with Sign Extend Operation: (Source with sign extension) → Destination Assembler Syntax: MVS y,Dx Attributes: Size = byte, word Description: Sign-extend the source operand and move to the destination register. For the byte operation, bit 7 of the source is copied to bits 31–8 of the destination. For the word operation, bit 15 of the source is copied to bits 31-16 of the destination.
ColdFire Instruction Set Architecture Enhancements MVZ MVZ Move with Zero-Fill Operation: (Source with zero fill) → Destination Assembler Syntax MVZ y,Dx Attributes: Size = byte, word Description—Zero-fill the source operand and move to the destination register. For the byte operation, the source operand is moved to bits 7–0 of the destination and bits 31–8 are filled with zeros.
ColdFire Instruction Set Architecture Enhancements SATS SATS Signed Saturate Operation: If CCR.V == 1, then if Dx[31] == 0, then Dx[31:0] = 0x80000000 else Dx[31:0] = 0x7FFFFFFF else Dx[31:0] is unchanged Assembler Syntax: SATS Dx Attributes: Size = long Description: Update the destination register only if the overflow bit of the CCR is set. If the operand is negative, then set the result to greatest positive number, otherwise set the result to the largest negative value.
ColdFire Instruction Set Architecture Enhancements TAS TAS Test and Set an Operand Operation: Destination Tested → CCR; 1 → bit 7 of Destination Assembler Syntax: TAS x Attributes: Size = byte Description: Tests and sets the byte operand addressed by the effective address field. The instruction tests the current value of the operand and sets the N and Z condition code bits appropriately. TAS also sets the high-order bit of the operand.
ColdFire Instruction Set Architecture Enhancements 2-52 MCF5407 User’s Manual
Chapter 3 Hardware Multiply/Accumulate (MAC) Unit This chapter describes the MCF5407 multiply/accumulate (MAC) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). 3.1 Overview The MAC unit provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family.
Overview Operand Y Operand X X Shift 0,1,-1 +/- Accumulator Figure 3-1. ColdFire MAC Multiplication and Accumulation The MAC unit is an extension of the basic multiplier found on most microprocessors. It can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application constraints.
Overview These registers are described as follows: • • • Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations. Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory.
Overview The need to move large amounts of data quickly can limit throughput in DSP engines. However, data can be moved efficiently by using the MOVEM instruction, which automatically generates line-sized burst references and is ideal for filling registers quickly with input data, filter coefficients, and output data. Loading an operand from memory into a register during a MAC operation makes some DSP operations, especially filtering and convolution, more manageable.
MAC Instruction Execution Timings • • Two’s complement unsigned integer: In this format, an N-bit operand represents a number within the range 0 < operand < 2N - 1. The binary point is to the right of the least significant bit. Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining bits signify the first N-1 bits after the binary point. Given an N-bit number, aN-1aN-2aN-3...
MAC Instruction Execution Timings Table 3-3. MAC Move Instruction Execution Times Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # move.l ,ACC 1(0/0) — — — — — — 1(0/0) move.l ,MACSR 6(0/0) — — — — — — 6(0/0) move.l ,MASK 5(0/0) — — — — — — 5(0/0) move.l ACC,Rx 1(0/0) — — — — — — — move.l MACSR,CCR 1(0/0) — — — — — — — move.l MACSR,Rx 1(0/0) — — — — — — — move.
Chapter 4 Local Memory This chapter describes the MCF5407 implementation of the ColdFire Version 4 local memory specification. It consists of two major sections. • • Section 4.2, “SRAM Overview,” describes the MCF5407 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM. Section 4.
SRAM Operation 0-modulo-2K location in the 4-Gbyte address space and configured to respond to either instruction or data accesses. Time-critical functions can be mapped into instruction memory and the system stack. Other heavily-referenced data can be mapped into data memory. The following summarizes features of the MCF5407 SRAM implementation: • • • • • • Two 2-Kbyte SRAMs, organized as 512 x 32 bits Single-cycle throughput. When the pipeline is full, one access can occur per clock cycle.
SRAM Programming Model Accesses are attempted in the following order: 1. SRAM 2. Cache (if space is defined as cacheable) 3. External access 4.4 SRAM Programming Model The SRAM programming model consists of RAMBAR0 and RAMBAR1. 4.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1) The SRAM modules are configured through the RAMBARs, shown in Figure 4-1. • • • • Each RAMBAR holds the base address of the SRAM. The MOVEC instruction provides write-only access to this register from the processor.
SRAM Initialization Table 4-1. RAMBARn Field Description (Continued) Bits Name Description 6 — Reserved, should be cleared. 5–1 C/I, SC, SD, UC, UD Address space masks (ASn). These fields allow certain types of accesses to be masked, or inhibited from accessing the SRAM module. These bits are useful for power management as described in Section 4.6, “Power Management.” In particular, C/I is typically set. The address space mask bits are follows: C/I = CPU space/interrupt acknowledge cycle mask.
SRAM Initialization 2. Read the source data and write it to the SRAM. Various instructions support this function, including memory-to-memory move instructions and the move multiple instruction (MOVEM). MOVEM is optimized to generate line-sized burst fetches on line-aligned addresses, so it generally provides maximum performance. 3. After the data is loaded into the SRAM, it may be appropriate to revise the RAMBAR attribute bits, including the write-protect and address space mask fields.
Power Management ; ; ; ; ; ; ; +0 +4 +8 +12 +16 +20 +24 loop: saved d2 saved d3 saved d4 returnPc pointer to source operand destinationOffset bytesToMove move.l movec.l RAMBASE+RAMFLAGS,a0 a0,rambar0 ;define RAMBAR0 contents ;load it move.l 16(a7),a0 ;load argument defining *src lea.l add.l RAMBASE,a1 20(a7),a1 ;memory pointer to RAM base ;include destinationOffset move.l asr.l 24(a7),d4 #4,d4 ;load byte count ;divide by 16 to convert to loop count .align movem.l movem.l lea.l lea.l subq.
Cache Overview The MCF5407 implements a special branch instruction cache for accelerating branches, enabled by a bit in the cache access control register (CACR[BEC]). The branch cache is described in Section 2.1.2.1.1, “Branch Acceleration.” The MCF5407 processor’s Harvard memory structure includes an 8-Kbyte data cache and a 16-Kbyte instruction cache. Both are nonblocking and 4-way set-associative with a 16-byte line.
Cache Organization 4.8 Cache Organization A four-way set associative cache is organized as four ways (levels). There are 128 sets in the 8-Kbyte data cache with each line containing 16 bytes (4 longwords). The 16-Kbyte instruction cache has 256 sets. Entire cache lines are loaded from memory by burst-mode accesses that cache 4 longwords of data or instructions. All 4 longwords must be loaded for the cache line to be valid. Figure 4-3 shows data cache organization as well as terminology used.
Cache Organization 4.8.2 The Cache at Start-Up As Figure 4-4 (A) shows, after power-up, cache contents are undefined; V and M may be set on some lines even though the cache may not contain the appropriate data for start up. Because reset and power-up do not invalidate cache lines automatically, the cache should be cleared explicitly by setting CACR[DCINVA,ICINVA] before the cache is enabled (B). After the entire cache is flushed, cacheable entries are loaded first in way 0.
Cache Organization Invalid (V = 0) Valid, not modified (V = 1, M = 0) Valid, modified (V = 1, M = 1) A:Cache population at start-up B:Cache after invalidation, C:Cache after loads in before it is enabled Way 0 D:First load in Way 1 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 At reset, cache contents are indeterminate; V and M may be set. The cache should be cleared explicitly by setting CACR[DCINVA] before the cache is enabled.
Cache Operation 4.9 Cache Operation Figure 4-5 shows the general flow of a caching operation using the 8-Kbyte data cache as an example. The discussion in this chapter assumes a data cache. Instruction cache operations are similar except that there is no support for writing to the cache; therefore such notions of modified cache lines and write allocation do not apply.
Cache Operation To allocate a cache entry, the cache set index selects one of the cache’s 128 sets. The cache control logic looks for an invalid cache line to use for the new entry. If none is available, the cache controller uses a pseudo-round-robin replacement algorithm to choose the line to be deallocated and replaced. First the cache controller looks for an invalid line, with way 0 the highest priority. If all lines have valid data, a 2-bit replacement counter is used to choose the way.
Cache Operation Write accesses designated as cache-inhibited by the CACR or ACR bypass the cache and perform a corresponding external write. Normally, cache-inhibited reads bypass the cache and are performed on the external bus. The exception to this normal operation occurs when all of the following conditions are true during a cache-inhibited read: • • • The cache-inhibited fill buffer bit, CACR[DNFB], is set. The access is an instruction read. The access is normal (that is, transfer type (TT) equals 0).
Cache Operation 4.9.1.1 Cacheable Accesses If ACRn[CM] or the default field of the CACR indicates write-through or copyback, the access is cacheable. A read access to a write-through or copyback region is read from the cache if matching data is found. Otherwise, the data is read from memory and the cache is updated.
Cache Operation In determining whether a memory location is cacheable or cache-inhibited, the CPU checks memory-control registers in the following order: 1. 2. 3. 4. RAMBARs ACR0 and ACR2 ACR1 and ACR3 If an access does not hit in the RAMBARs or the ACRs, the default is provided for all accesses in CACR. Cache-inhibited write accesses bypass the cache and a corresponding external write is performed.
Cache Operation 4.9.3.1 Read Miss A processor read that misses in the cache requests the cache controller to generate a bus transaction. This bus transaction reads the needed line from memory and supplies the required data to the processor core. The line is placed in the cache in the valid state. 4.9.3.2 Write Miss (Data Cache Only) The cache controller handles processor writes that miss in the data cache differently for write-through and copyback regions.
Cache Operation 4.9.3.4 Write Hit (Data Cache Only) The cache controller handles processor writes that hit in the data cache differently for write-through and copyback regions. For write hits to a write-through region, portions of cache lines corresponding to the size of the access are updated with the data. The data is also written to external memory. The cache line state is unchanged. For copyback accesses, the cache controller updates the cache line and sets the M bit for the line.
Cache Operation 4.9.5.2 Cache Pushes Cache pushes occur for line replacement and as required for the execution of the CPUSHL instruction. To reduce the requested data’s latency in the new line, the modified line being replaced is temporarily placed in the push buffer while the new line is fetched from memory. After the bus transfer for the new line completes, the modified cache line is written back to memory and the push buffer is invalidated. 4.9.5.2.
Cache Operation another cache fill is required (for example, cache miss to process) during the continued instruction execution by the processor pipeline, the pipeline stalls until the push and store buffers are empty, then generate the required external bus transaction. Supervisor instructions, the NOP instruction, and exception processing synchronize the processor core and guarantee the push and store buffers are empty before proceeding.
Cache Operation Invalid (V = 0) Valid, not modified (V = 1, M = 0) Valid, modified (V = 1, M = 1) A:Ways 0 and 1 are filled. Ways 2 and 3 are invalid. B:CACR[DHLCK] is set, locking ways 0 and 1. C:When a set in Way 2 is D:Write hits to ways 0 occupied, the set in way 3 and 1 update cache is used for a cacheable lines. access. Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 After CACR[DHLCK] is set, subsequent cache accesses go to ways 2 and 3.
Cache Registers 4.10 Cache Registers This section describes the MCF5407 implementation of the Version 4 cache registers. 4.10.1 Cache Control Register (CACR) The CACR in Figure 4-8 contains bits for configuring the cache. It can be written by the MOVEC register instruction and can be read or written from the debug facility. A hardware reset clears CACR, which disables the cache; however, reset does not affect the tags, state information, or data in the cache.
Cache Registers Table 4-4. CACR Field Descriptions (Continued) Bits Name Description 27 DHLCK Half-data cache lock mode 0 Normal operation. The cache allocates the lowest invalid way. If all ways are valid, the cache allocates the way pointed at by the counter and then increments this counter modulo-4. 1 Half-cache operation.
Cache Registers Table 4-4. CACR Field Descriptions (Continued) Bits Name Description 11 IHLCK Instruction cache half-lock. 0 Normal operation. The cache allocates to the lowest invalid way; if all ways are valid, the cache allocates to the way pointed at by the round-robin counter and then increments this counter modulo-4. 1 Half cache operation.
Cache Management 31 Field 24 23 Address Base Reset 16 15 14 13 12 Address Mask Uninitialized R/W E S 7 6 — 0 5 CM 4 3 — 2 W1 1 0 — Uninitialized Write (R/W by debug module) Rc ACR0: 0x004; ACR1: 0x005; ACR2: 0x006; ACR3: 0x007 1 Reserved in ACR2 and ACR3. Figure 4-9. Access Control Register Format (ACRn) Table 4-5 describes ACRn fields. I Table 4-5. ACRn Field Descriptions Bits Name Description 31–24 Address base Address base. Compared with address bits A[31:24].
Cache Management The privileged CPUSHL instruction supports cache management by selectively pushing and invalidating cache lines. The address register used with CPUSHL directly addresses the cache’s directory array. The CPUSHL instruction flushes a cache line. The value of CACR[DDPI,IDPI] determines whether CPUSHL invalidates a cache line after it is pushed.
Cache Management addq.l move.l cmpi.l bne rts #1,d0 d0,a0 #4,d0 setloop ;increment to next way ;set = 0, way = d0 ;flushed all the ways? The following CACR loads assume the instruction cache has been invalidated, the default instruction cache mode is cacheable, and the default data cache mode is copyback. dataCacheLoadAndLock: move.l movec #0xa3080800,d0; enable and invalidate data cache ... d0,cacr ; ... in the CACR The following code preloads half of the data cache (4 Kbytes).
Cache Operation Summary ;instruction cache lea 16(a0),a0 ;increment address to next line subq.l #1,d0 ;decrement loop counter bne.b instCacheLoop ;if done, then exit, else continue ; A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache. ; lock it! move.l movec rts #0xa2088800,d0 d0,cacr ;set the instruction cache lock bit ;in the CACR 4.12 Cache Operation Summary This section gives operational details for the cache and presents instruction and data cache-line state diagrams. 4.
Cache Operation Summary Table 4-6. Instruction Cache Line State Transitions (Continued) Current State Access Invalid (V = 0) Valid (V = 1) Cache invalidate II5 No action; stay in invalid state. IV5 No action; go to invalid state. Cache push II6, No action; II7 stay in invalid state. IV6 No action; go to invalid state. IV7 No action; stay in valid state. 4.12.
Cache Operation Summary Figure 4-14 shows the two possible states for a cache line in write-through mode. WV1—CPU read miss WV2—CPU read hit WV3—CPU write miss WV4—CPU write hit WV7—CPUSHL & DDPI WI3—CPU write miss WI5—DCINVA WI6—CPUSHL & DDPI WI7—CPUSHL & DDPI WI1—CPU read miss Invalid V=0 Valid V=1 WV5—DCINVA WV6—CPUSHL & DDPI Figure 4-14. Data Cache Line State Diagram—Write-Through Mode Table 4-7 describes data cache line transitions and the accesses that cause them. Table 4-7.
Cache Operation Summary Table 4-7. Data Cache Line State Transitions (Continued) Current State Access Invalid (V = 0) Write hit (writethrough) WI4 Not possible. Valid (V = 1, M = 0) WV4 Write data to memory and to cache; stay in valid state. Modified (V = 1, M = 1) WD4 Write data to memory and to cache; go to valid state. Cache mode changed for the region corresponding to this line. To avoid this state, execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
Cache Operation Summary Table 4-9. Data Cache Line State Transitions (Current State Valid) Access Response Read miss (C,W)V1 Read new line from memory and update cache; supply data to processor; stay in valid state. Read hit (C,W)V2 Supply data to processor; stay in valid state. Write miss (copyback) CV3 Read new line from memory and update cache; write data to cache; go to modified state. Write miss (write-through) WV3 Write data to memory; stay in valid state.
Cache Initialization Code Table 4-10. Data Cache Line State Transitions (Current State Modified) (Continued) Access Response Cache invalidate CD5 No action (modified data lost); go to invalid state. Cache push CD6 Push modified line to memory; go to invalid state. Cache push CD7 Push modified line to memory; go to valid state. 4.13 Cache Initialization Code The following example sets up the cache for FLASH or ROM space only. move.
Chapter 5 Debug Support This chapter describes the Revision C enhanced hardware debug support in the MCF5407. This revision of the ColdFire debug architecture encompasses the two earlier revisions. 5.1 Overview The debug module is shown in Figure 5-1. High-speed local bus ColdFire CPU Core Debug Module Control BKPT Trace Port PSTDDATA[7:0] PSTCLK Communication Port DSCLK, DSI, DSO Figure 5-1.
Signal Descriptions The Version 2 ColdFire core implemented the original debug architecture, now called Revision A. Based on feedback from customers and third-party developers, enhancements have been added to succeeding generations of ColdFire cores.
Signal Descriptions Figure 5-2 shows PSTCLK timing. PSTCLK PSTDDATA Figure 5-2. PSTCLK Timing 5.2.1 Processor Status/Debug Data (PSTDDATA[7:0]) Processor status data outputs are used to indicate both processor status and captured address and data values. They operate at half the processor’s frequency.
Real-Time Trace Support Table 5-3 shows the case where a PSTDDATA module captures a memory operand on a simple load instruction: mov.l ,Rx. Table 5-3. PSTDDATA: Data Operand Captured Cycle T PSTDDATA[7:0] {PST for mov.
Real-Time Trace Support Execution speed is affected only when three storage elements have valid data to be dumped to the PSTDDATA port. This occurs only when two values are captured simultaneously in a read-modify-write operation; the core stalls until two FIFO entries are available. Table 5-4 shows the encoding of these signals. Table 5-4. Processor Status Encoding PST[3:0] Definition Hex Binary 0x0 0000 Continue execution. Many instructions execute in one processor cycle.
Real-Time Trace Support 5.3.1 Begin Execution of Taken Branch (PST = 0x5) PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed on PSTDDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data output. Bytes are displayed in least-to-most-significant order.
Real-Time Trace Support 5.3.2 Processor Stopped or Breakpoint State Change (PST = 0xE) The 0xE encoding is generated either as a one- or multiple-cycle issue as follows: • • When the MCF5407 is stopped by a STOP instruction, this encoding appears in multiple-cycle format. The ColdFire processor remains stopped until an interrupt occurs, thus PSTDDATA outputs display 0xE until stopped mode is exited.
Programming Model Two scenarios exist for data—0xFFFF_FFFF • • A B marker occurs on the left nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xBF 0xFF 0xFF 0xFF 0xFX (X indicates that the next PST value is guaranteed to not be 0xF.) A B marker occurs on the right nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xYB 0xFF 0xFF 0xFF 0xFF 0xXY (X indicates the PST value is guaranteed not to be 0xF, and Y signifies a PSTDDATA value that doesn’t affect the 0xFF count.
Programming Model 31 15 31 15 31 15 31 7 0 AATR Address attribute trigger register ABLR ABHR Address low breakpoint register Address high breakpoint register AATR1 Address 1 attribute register 0 7 15 0 0 ABLR1 Address low breakpoint 1 register ABHR1 Address high breakpoint 1 register 31 15 31 15 0 31 15 0 31 7 15 0 BAAR BDM address attribute register CSR Configuration/status register DBR DBMR Data breakpoint register Data breakpoint mask register 0 DBR1 Data breakpoin
Programming Model Table 5-6. BDM/Breakpoint Registers (Continued) DRc[4–0] Register Name Abbreviation Initial State Page 0x07 Trigger definition register TDR 0x0000_0000 p. 5-18 0x08 Program counter breakpoint register PBR — p. 5-16 0x09 Program counter breakpoint mask register PBMR — p. 5-16 — — — Address breakpoint high register ABHR — p. 5-12 0x0D Address breakpoint low register ABLR — p. 5-12 0x0E Data breakpoint register DBR — p.
Programming Model 15 Field RM Reset 14 13 SZM 12 11 TTM 10 9 TMM 8 7 6 R 5 SZ 4 3 2 TT 1 0 TM 0000_0000_0000_0101 R/W AATR and AATR1 are accessible in supervisor mode as debug control register 0x06 and 0x16 respectively, and using the WDEBUG instruction and through the BDM port using the WDMREG command. DRc[4–0] 0x06 (AATR); 0x16 (AATR1) Figure 5-6. Address Attribute Trigger Registers (AATR, AATR1) Table 5-7 describes AATR and AATR1 fields. Table 5-7.
Programming Model 5.4.2 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) The address breakpoint low and high registers (ABLR, ABLR1, ABHR, and ABHR1), Figure 5-7, define regions in the processor’s data address space that can be used as part of the trigger. These register values are compared with the address for each transfer on the processor’s high-speed local bus. TDR determines if the trigger is in the address in ABLR or either inside or outside of the range bound by ABLR and ABHR.
Programming Model 7 Field 6 5 R 4 3 SZ 2 1 TT Reset 0 TM 0000_0101 R/W BAAR[R,SZ] are loaded directly from the BDM command; BAAR[TT,TM] can be programmed as debug control register 0x05 from the external development system. For compatibility with Rev. A, BAAR is loaded each time AATR is written. DRc[4–0] 0x05 Figure 5-8. BDM Address Attribute Register (BAAR) Table 5-10 describes BAAR fields. Table 5-10.
Programming Model Table 5-11 describes CSR fields. Table 5-11. CSR Field Descriptions Bit 31–28 Name Description BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. Also output on PSTDDATA when it is not displaying PST or other processor data. BSTAT is cleared by a TDR or XTDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled.
Programming Model Table 5-11. CSR Field Descriptions (Continued) Bit Name Description 12–11 DDC Debug data control. Controls operand data capture for PSTDDATA, which displays the number of bytes defined by the operand reference size before the actual data; byte displays 8 bits, word displays 16 bits, and long displays 32 bits (one nibble at a time across multiple clock cycles). See Table 5-4. 00 No operand data is displayed. 01 Capture all write data. 10 Capture all read data.
Programming Model 31 0 Field Data (DBR/DBR1); Mask (DBMR/DBMR1) Reset Uninitialized R/W DBR and DBR1 are accessible in supervisor mode as debug control register 0x0E and 0x1E, using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands. DBMR and DBMR1 are accessible in supervisor mode as debug control register 0x0F and 0x0F1 using the WDEBUG instruction and via the BDM port using the WDMREG command.
Programming Model program counter register when the appropriate valid bit is set and TDR and/or XTDR are configured appropriately. PBR bits are masked by clearing corresponding PBMR bits. Results are compared with the processor’s program counter register, as defined in TDR and/or XTDR. PBR1–PBR3 are not masked. Figure 5-11 shows the PC breakpoint register. 31 1 0 Field Program Counter V1 Reset — 0 R/W Write.
Programming Model 5.4.7 Trigger Definition Register (TDR) The TDR, shown in Table 5-13, configures the operation of the hardware breakpoint logic that corresponds with the ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug module. In conjunction with the XTDR and its associated debug registers, TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured as one- or two-level triggers.
Programming Model Table 5-17. TDR Field Descriptions Bits Name Description 31–30 TRC Trigger response control. Determines how the processor responds to a completed trigger condition. The trigger response is always displayed on PSTDDATA. 00 Display on PSTDDATA only 01 Processor halt 10 Debug interrupt 11 Reserved 29/13 EBL Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] or XTDR[EBL] enables a breakpoint trigger; clearing both disables all breakpoints.
Programming Model NOTE: The debug module has no hardware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR and XTDR (by clearing TDR[29,13] and XTDR[29,13]) before defining triggers. A write to the XTDR clears the trigger status bits, CSR[BSTAT]. Section 5.4.9, “Resulting Set of Possible Trigger Combinations,” describes how to handle multiple breakpoint conditions.
Programming Model Table 5-18. XTDR Field Descriptions (Continued) Bits Name Description 21/5 DI Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value other than the DBR1 contents. 20–18/ 4–2 EAx Enable address bits. Setting an EAx bit enables the corresponding address breakpoint. If all three bits are cleared, this breakpoint is disabled.
Background Debug Mode (BDM) then if (PC_breakpoint) if (Address_breakpoint {&& Data_breakpoint}) then if (PC_breakpoint || Address1_breakpoint{&& Data1_breakpoint}) if (Address1_breakpoint {&& Data1_breakpoint}) then if (PC_breakpoint || Address_breakpoint{&& Data_breakpoint}) In this example, PC_breakpoint is the logical summation of the PBR/PBMR, PBR1, PBR2, and PBR3 breakpoint registers; Address_breakpoint is a function of ABHR, ABLR, and AATR; Data_breakpoint is a function of DBR and DBMR; Address
Background Debug Mode (BDM) 4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt condition is postponed until the processor core samples for halts/interrupts. The processor samples for these conditions once during the execution of each instruction. If there is a pending halt condition at the sample time, the processor suspends execution and enters the halted state.
Background Debug Mode (BDM) • A B marker occurs on the right nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xYB 0xFF 0xFF 0xFF 0xFF 0xXY (X indicates that the PST value is guaranteed to not be 0xF; and Y indicates a PSTDDATA value that doesn’t affect the 0xFF count). Thus, a count of either nine or more sequential single 0xF values or five or more sequential 0xFF values signifies the HALT condition. 5.5.
Background Debug Mode (BDM) DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor CLK as well as the DSI. DSO is delayed from the DSCLK-enabled CLK rising edge (registered after a BDM state machine state change). All events in the debug module’s serial state machine are based on the processor clock rising edge. DSCLK must also be sampled low (on a positive edge of CLK) between each bit exchange. The MSB is transferred first.
Background Debug Mode (BDM) 5.5.2.2 Transmit Packet Format The basic transmit packet, Figure 5-17, consists of 16 data bits and 1 control bit. 16 15 0 C D[15:0] Figure 5-17. Transmit BDM Packet Table 5-20 describes transmit BDM packet fields. Table 5-20. Transmit BDM Packet Field Description Bits Name 16 C 15–0 Data Description Control. This bit is reserved. Command and data transfers initiated by the development system should clear C.
Background Debug Mode (BDM) Table 5-21. BDM Command Summary (Continued) CPU State1 Section Capture the current PC and display it on the PSTDDATA output pins. Parallel 5.5.3.3.9 0x0001 Read control RCREG register Read the system control register. Halted 5.5.3.3.10 0x2980 Write control WCREG register Write the operand data to the system control register. Halted 5.5.3.3.11 0x2880 Read debug module register RDMREG Read the debug module register. Parallel 5.5.3.3.
Background Debug Mode (BDM) Table 5-22. BDM Field Descriptions (Continued) Bit 7–6 Name Description Operand Size Operand data size for sized operations. Addresses are expressed as 32-bit absolute values. Note that a command performing a byte-sized memory read leaves the upper 8 bits of the response data undefined. Referenced data is returned in the lower 8 bits of the response.
Background Debug Mode (BDM) COMMANDS TRANSMITTED TO THE DEBUG MODULE COMMAND CODE TRANSMITTED DURING THIS CYCLE HIGH-ORDER 16 BITS OF MEMORY ADDRESS LOW-ORDER 16 BITS OF MEMORY ADDRESS NONSERIAL-RELATED ACTIVITY SEQUENCE TAKEN IF OPERATION HAS NOT COMPLETED READ (LONG) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" READ MEMORY LOCATION XXX "NOT READY" XXXXX XXX MS RESULT XXX BERR NEXT COMMAND CODE NEXT CMD LS RESULT NEXT CMD "NOT READY" DATA UNUSED FROM THIS TRANSFE
Background Debug Mode (BDM) • Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is sent to the debug module during the final transfer.
Background Debug Mode (BDM) 5.5.3.3.2 Write A/D Register (WAREG/WDREG) The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: 15 Command 12 0x2 11 8 7 0x0 Result 4 0x8 3 A/D 2 0 Register D[31:16] D[15:0] Figure 5-22.
Background Debug Mode (BDM) 5.5.3.3.3 Read Memory Location (READ) Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.
Background Debug Mode (BDM) 5.5.3.3.4 Write Memory Location (WRITE) Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.
Background Debug Mode (BDM) Command Sequence: WRITE (B/W) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" XXX CMD NEXT "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" WRITE (LONG) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" MS DATA "NOT READY" LS DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" XXX CMD NEXT "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" Figure 5-27.
Background Debug Mode (BDM) 5.5.3.3.5 Dump Memory Block (DUMP) is used with the READ command to access large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. If an initial READ is not executed before the first DUMP, an illegal command response is returned. The DUMP command retrieves subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register.
Background Debug Mode (BDM) Command Sequence: READ MEMORY LOCATION DUMP (B/W) ??? XXX "NOT READY" NEXT CMD RESULT XXX "ILLEGAL" NEXT CMD "NOT READY" READ MEMORY LOCATION DUMP (LONG) ??? XXX "ILLEGAL" XXX BERR NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD "NOT READY" NEXT CMD MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD "NOT READY" Figure 5-29. DUMP Command Sequence Operand Data: None Result Data: Requested data is returned as either a word or longword.
Background Debug Mode (BDM) 5.5.3.3.6 Fill Memory Block (FILL) A FILL command is used with the WRITE command to access large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. The FILL command writes subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register after the memory write.
Background Debug Mode (BDM) Command Sequence: FILL FILL(LONG) (B/W) ??? MS DATA "NOT READY" XXX "ILLEGAL" LS DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" NEXT CMD "CMD COMPLETE" NEXT CMD "NOT READY" XXX BERR FILL(LONG) (B/W) FILL ??? DATA "NOT READY" WRITE MEMORY LOCATION XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" Figure 5-31.
Background Debug Mode (BDM) 5.5.3.3.7 Resume Execution (GO) The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes. If a GO command is issued and the CPU is not halted, the command is ignored.
Background Debug Mode (BDM) 5.5.3.3.8 No Operation (NOP) NOP performs no operation and may be used as a null command where required. Command Formats: 15 12 11 8 0x0 0x0 7 4 0x0 3 0 0x0 Figure 5-34. NOP Command Format Command Sequence: NOP ??? NEXT CMD "CMD COMPLETE" Figure 5-35. NOP Command Sequence Operand Data: None Result Data: The command-complete response, 0xFFFF (with S cleared), is returned during the next shift operation.
Background Debug Mode (BDM) 5.5.3.3.9 Synchronize PC to the PSTDDATA Lines (SYNC_PC) The SYNC_PC command captures the current PC and displays it on the PSTDDATA outputs. After the debug module receives the command, it sends a signal to the ColdFire processor that the current PC must be displayed. The processor then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of CSR[BTB]. The specific sequence of PSTDDATA values is as follows: 1.
Background Debug Mode (BDM) 5.5.3.3.10 Read Control Register (RCREG) Read the selected control register and return the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. The 12-bit Rc field is the same as that used by the MOVEC instruction.
Background Debug Mode (BDM) 5.5.3.3.11 Write Control Register (WCREG) The operand (longword) data is written to the specified control register. The write alters all 32 register bits. Command/Result Formats: 15 Command 12 11 8 7 4 3 0 0x2 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 Rc Result D[31:16] D[15:0] Figure 5-40.
Background Debug Mode (BDM) 5.5.3.3.12 Read Debug Module Register (RDMREG) Read the selected debug module register and return the 32-bit result. The only valid register selection for the RDMREG command is CSR (DRc = 0x00). Note that this read of the CSR clears the trigger status bits (CSR[BSTAT]) if either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled.
Real-Time Debug Support 5.5.3.3.13 Write Debug Module Register (WDMREG) The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction. Command Format: Figure 5-44.
Real-Time Debug Support 5.6.1 Theory of Operation Breakpoint hardware can be configured to respond to triggers in several ways. The response desired is programmed into TDR. As shown in Table 5-25, when a breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the PSTDDATA output port when it is not displaying captured processor status, operands, or branch addresses. See Section 5.3.2, “Processor Stopped or Breakpoint State Change (PST = 0xE).” Table 5-25.
Real-Time Debug Support processing begins. After the standard 8-byte exception stack is created, the processor fetches a unique exception vector from the vector table. Table 5-26 describes the two unique entries that distinguish PC breakpoints from other trigger events. Table 5-26.
Real-Time Debug Support development system can use BDM commands to read the reserved memory locations. The generation of another debug interrupt during the first instruction after the RTE exits emulator mode is inhibited. This behavior is consistent with the existing logic involving trace mode where the first instruction executes before another trace exception is generated.
Motorola-Recommended BDM Pinout Breakpoint registers must be carefully configured in a development system if the processor is executing. The debug module contains no hardware interlocks, so TDR and XTDR should be disabled while breakpoint registers are loaded, after which TDR and XTDR can be written to define the exact trigger. This prevents spurious breakpoint triggers.
Debug C Definition of PSTDDATA Outputs 5.8.1 User Instruction Set Table 5-27 shows the PSTDDATA specification for user-mode instructions. Table 5-27. PSTDDATA Specification for User-Mode Instructions Instruction Syntax PSTDDATA add.l y,Rx PSTDDATA = 1, {B, source operand} add.l Dy,x PSTDDATA = 1, {B, source}, {B, destination} addi.l #imm,Dx PSTDDATA = 1 addq.l #imm,x PSTDDATA = 1, {B, source}, {B, destination} addx.l Dy,Dx PSTDDATA = 1 and.
Debug C Definition of PSTDDATA Outputs Table 5-27. PSTDDATA Specification for User-Mode Instructions (Continued) Instruction Syntax PSTDDATA divu.w y,Dx PSTDDATA = 1, {9, source operand} eor.l Dy,x PSTDDATA = 1, {B, source}, {B, destination} eori.l #imm,Dx PSTDDATA = 1 ext.w Dx PSTDDATA = 1 ext.l Dx PSTDDATA = 1 extb.
Debug C Definition of PSTDDATA Outputs Table 5-27. PSTDDATA Specification for User-Mode Instructions (Continued) Instruction Syntax PSTDDATA muls.w y,Dx PSTDDATA = 1, {9, source operand} mulu.w y,Dx PSTDDATA = 1, {9, source operand} muls.l y,Dx PSTDDATA = 1, {B, source operand} mulu.l y,Dx PSTDDATA = 1, {B, source operand} mvs.b y,Dx PSTDDATA = 1, {8, source operand} mvs.w y,Dx PSTDDATA = 1, {9, source operand} mvz.
Debug C Definition of PSTDDATA Outputs Table 5-27. PSTDDATA Specification for User-Mode Instructions (Continued) Instruction Syntax PSTDDATA tst.w x PSTDDATA = 1, {9, source operand} tst.l x PSTDDATA = 1, {B, source operand} unlk Ax PSTDDATA = 1, {B, destination operand} wddata.b y PSTDDATA = 4, 8, source operand wddata.w y PSTDDATA = 4, 9, source operand wddata.
Debug C Definition of PSTDDATA Outputs Table 5-28. PSTDDATA Specification for Supervisor-Mode Instructions Instruction Syntax PSTDDATA cpushl PSTDDATA = 1 halt PSTDDATA = 1, PSTDDATA = F intouch PSTDDATA = 1 move.w SR,Dx move.
Part II System Integration Module (SIM) Intended Audience Part II is intended for users who need to understand the interface between the ColdFire core processor complex, described in Part I, and internal peripheral devices, described in Part III.
includes a description of signals involved in DRAM operations. The remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. Suggested Reading The following literature may be helpful with respect to the topics in Part II: The I2C Bus Specification, Version 2.1 (January 2000) • Acronyms and Abbreviations Table II-i contains acronyms and abbreviations are used in Part II. Table II-i.
Table II-i. Acronyms and Abbreviated Terms (Continued) Term Meaning NOP No operation PCLK Processor clock PLL Phase-locked loop POR Power-on reset Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Part II.
II-iv MCF5407 User’s Manual
Chapter 6 SIM Overview This chapter provides detailed operation information regarding the system integration module (SIM). It describes the SIM programming model, bus arbitration, and system-protection functions for the MCF5407. 6.1 Features The SIM, shown in Figure 6-1, provides overall control of the bus and serves as the interface between the ColdFire core processor complex and the internal peripheral devices.
Features The following is a list of the key SIM features: • • • • • • • 6-2 Module base address register (MBAR) — Base address location of all internal peripherals and SIM resources — Address space masking to internal peripherals and SIM resources Phase-locked loop (PLL) clock control register (PLLCR) for CPU STOP instruction — Control for turning off clocks to core and interrupt levels that turn clocks back on Chapter 7, “Phase-Locked Loop (PLL).
Programming Model 6.2 Programming Model The following sections describe the registers incorporated into the SIM. 6.2.1 SIM Register Memory Map Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM are memory-mapped registers offset from the MBAR address pointer defined in MBAR[BA]. This supervisor-level register is described in Section 6.2.2, “Module Base Address Register (MBAR).
Programming Model Table 6-1. SIM Registers (Continued) MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x04C Software watchdog timer (ICR0) [p. 9-3] Timer0 (ICR1) [p. 9-3] Timer1 (ICR2) [p. 9-3] I2C (ICR3) [p. 9-3] 0x050 UART0 (ICR4) [p. 9-3] UART1 (ICR5) [p. 9-3] DMA0 (ICR6) [p. 9-3] DMA1 (ICR7) [p. 9-3] 0x054 DMA2 (ICR8) [p. 9-3] DMA3 (ICR9) [p. 9-3] Reserved 6.2.
Programming Model Table 6-2 describes MBAR fields. Table 6-2. MBAR Field Descriptions Bits Field 31–12 BA 11–9 — 8 WP Description Base address. Defines the base address for a 4-Kbyte address range. Reserved, should be cleared. Write protect. Mask bit for write cycles in the MBAR-mapped register address range. 0 Module address range is read/write. 1 Module address range is read only. 7 — Reserved, should be cleared. 6 AM Alternate master mask.
Programming Model Table 6-3 describes RSR fields. Table 6-3. RSR Field Descriptions Bits Name 7 HRST 6 — 5 SWTR 4–0 — Description Hardware or system reset 1 An external device driving RSTI caused the last reset. Assertion of reset by an external device causes the core processor to take a reset exception. All registers in internal peripherals and the SIM are reset. Reserved, should be cleared. Software watchdog timer reset 1 The last reset was caused by the software watchdog timer.
Programming Model Code in the watchdog timer interrupt handler polls SYPCR[SWTAVAL] to determine if SWT TA was needed. If so, execute code to identify bad address. Code enables software watchdog timer interrupt and SWTA functionality by writing SYPCR. Problem: 1. Watchdog timer times out due to unterminated bus NOTE: The watchdog timer IRQ should be set to the highest level in the system. Software watchdog timer IRQ Timeout 2. Watchdog timer interrupt cannot be serviced due to hung bus cycle.
Programming Model 1. 2. 3. 4. Disable the software watchdog timer by clearing SYPCR[SWE]. Reset the counter by writing 0x55 and then 0xAA to SWSR. Update SYPCR[SWT,SWP]. Reenable the watchdog timer by setting SYPCR[SWE]. This can be done in step 3. 6.2.5 System Protection Control Register (SYPCR) The SYPCR, Figure 6-5, controls the software watchdog timer, timeout periods, and software watchdog timer transfer acknowledge.
Programming Model Table 6-4. SYPCR Field Descriptions (Continued) Bits Name Description 2 SWTA Software watchdog transfer acknowledge enable 0 SWTA transfer acknowledge disabled 1 SWTA asserts transfer acknowledge enabled. After one timeout period of the unacknowledged assertion of the software watchdog timer interrupt, the software watchdog transfer acknowledge asserts, which allows the watchdog timer to terminate a bus cycle and allow the IACK to occur.
Programming Model 6.2.8 PLL Clock Control for CPU STOP Instruction The SIM contains the PLL clock control register, which is described in detail in Section 7.2.4, “PLL Control Register (PLLCR).” PLLCR[ENBSTOP,PLLIPL] are significant to the operation of the SIM, and are described as follows: • • PLLCR[ENBSTOP] must be set for the ColdFire CPU STOP instruction to be acknowledged. This bit is cleared at reset and must be set for the MCF5407 to enter low-power modes.
Programming Model 6.2.10 Bus Arbitration Control This section describes the bus arbitration register and the four arbitration schemes. 6.2.10.1 Default Bus Master Park Register (MPARK) The MPARK, shown in Figure 6-9, determines the default bus master arbitration between internal transfers (core and DMA module) and between internal and external transfers to internal resources. This arbitration is needed because external masters can access internal registers within the MCF5407 peripherals.
Programming Model Table 6-6. MPARK Field Descriptions (Continued) Bits 3 2–0 Name Description SHOWDATA Enable internal register data bus to be driven on external bus. EARBCTRL must be set for this function to work. Section 6.2.10.1.2, “Arbitration between Internal and External Masters for Accessing Internal Resources,” describes the proper use of SHOWDATA. 0 Do not drive internal register data bus values to external bus. 1 Drive internal register data bus values to external bus.
Programming Model • Park on master core priority (PARK = 01)—The core retains bus mastership as long as it needs it. After it negates its internal bus request, the core does not have to rearbitrate for the bus unless the DMA module has requested the bus when it is idle. The DMA module can be granted bus mastership only when the core is not asserting its bus request. See Figure 6-11.
Programming Model • Park on current master priority (PARK = 11)—The current bus master retains mastership as long as it needs the bus. The other device can become the bus master only when the bus is idle. For example, if the core is bus master out of reset, it retains mastership as long as it needs the bus. It loses mastership only when it negates its bus request signal and the DMA asserts its internal bus request signal.
Programming Model • memories from responding to internal register transfers that go to the external bus. The AS signal and all chip-select-related strobe signals are not asserted. Do not immediately follow a cycle in which SHOWDATA is set with a cycle using fast termination. In multiple-master systems, disabling arbitration with EARBCTRL allows performance improvement because internal register bus transfer cycles do not interfere with the external bus.
Programming Model 6-16 MCF5407 User’s Manual
Chapter 7 Phase-Locked Loop (PLL) This chapter describes configuration and operation of the phase-locked loop (PLL) module. It describes in detail the registers and signals that support the PLL implementation. 7.1 Overview The basic features of the MCF5407 PLL implementation are as follows: • • The MCF5407 PLL is enhanced to support faster processor clock (PCLK) frequencies than the MCF5307. It also offers a wider range of clock input ratios.
PLL Operation Motorola recommends using CLKIN for the system clock. BCLKO is provided only for compatibility with slower MCF5307 designs. Regardless of the CLKIN frequency driven at power-up, CLKIN (and BCLKO) have the same ratio value to the PCLK. Although either signal can be used as a clock reference, CLKIN leaves more room to meet the bus specifications than BCLKO, which is generated as a phase-aligned signal to CLKIN. 7.1.
PLL Operation multiplied up as determined by the logic level of the multiplexed D[2:0]/DIVIDE[2:0] pins during reset to create PCLK. 7.2.3 Reduced-Power Mode The PCLK can be turned off in a predictable manner to conserve system power. To allow fast restart of the MCF5407 processor core, the PLL continues to operate at the frequency configured at reset. PCLK is disabled using the CPU STOP instruction and resumes normal operation on interrupt, as described in Section 7.2.4, “PLL Control Register (PLLCR).
PLL Port List 7.3 PLL Port List Table 7-3 describes PLL module inputs. Table 7-3. PLL Module Input SIgnals SIgnal Description CLKIN Input clock to the PLL. Input frequency must not be changed during operation. Changes are recognized only at reset. RSTI Active-low asynchronous input that, when asserted, indicates PLL is to enter reset mode. As long as RSTI is asserted, the PLL is held in reset and does not begin to lock.
Timing Relationships possible versions of CLKIN/BCLKO. This figure does not show the skew between CLKIN and PCLK, PSTCLK, and BCLKO. PSTCLK is half the frequency of PCLK. Similarly, the skew between PCLK and BCLKO is unspecified. PCLK PSTCLK CLKIN/BCLKO (/3) CLKIN/BCLKO (/4) CLKIN/BCLKO (/5) CLKIN/BCLKO (/6) NOTE: The clock signals are shown with edges aligned to show frequency relationships only. Actual signal edges have some skew between them. Figure 7-3. CLKIN, PCLK, PSTCLK, and BCLKO Timing 7.4.
PLL Power Supply Filter Circuit 50K CLKIN Cycle Lock Time >16 CLKS >10 CLKS CLKIN BCLKO PSTCLK RSTI D[7:0] D[7:0] latched on rising edge of CLKIN RSTO Figure 7-4. Reset and Initialization Timing 7.5 PLL Power Supply Filter Circuit To ensure PLL stability, the power supply to the PLL power pin should be filtered using a circuit similar to the one in Figure 7-5. The circuit should be placed as close as possible to the PLL power pin to ensure maximum noise filtering. 10 Ω Vdd PLL power pin 10 µF 0.
Chapter 8 I2C Module This chapter describes the MCF5407 I2C module, including I2C protocol, clock synchronization, and the registers in the I2C programing model. It also provides extensive programming examples. 8.1 Overview I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices.
Interface Features • • • • Start and stop signal generation/detection Repeated START signal generation Acknowledge bit generation/detection Bus-busy detection Figure 8-1 is a block diagram of the I2C module.
I2C System Configuration These registers are described in Section 8.5, “Programming Model.” 8.3 I2C System Configuration The I2C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. For I2C compliance, all devices connected to these two signals must have open drain or open collector outputs. (There is no such requirement for inputs.) The logic AND function is exercised on both lines with external pull-up resistors. Out of reset, the I2C default is as slave receiver.
I2C Protocol Each slave must have a unique address. An I2C master must not transmit an address that is the same as its slave address; it cannot be master and slave at the same time. The slave whose address matches that sent by the master pulls SDA low at the ninth clock (D) to return an acknowledge bit. 3. Data transfer—When successful slave addressing is achieved, the data transfer can proceed (E) on a byte-by-byte basis in the direction specified by the R/W bit sent by the calling master.
I2C Protocol synchronization procedure in which the low period equals the longest clock-low period among the devices and the high period equals the shortest. A data arbitration procedure determines the relative priority of competing devices. A device loses arbitration if it sends logic high while another sends logic low; it immediately switches to slave-receive mode and stops driving SDA. In this case, the transition from master to slave mode does not generate a STOP condition.
Programming Model the resulting SCL bus signal low period is stretched. 8.5 Programming Model Table 8-1 lists the configuration registers used in the I2C interface. Table 8-1. I2C Interface Memory Map MBAR Offset [31:24] [23:16] [15:8] 0x280 I2C address register (IADR) [p. 8-6] 0x284 I2C 0x288 I2C control register (I2CR) [p. 8-7] Reserved 0x28C I2C status register (I2SR) [p. 8-8] Reserved 0x290 I2C Reserved [7:0] Reserved frequency divider register (IFDR) [p.
Programming Model bit-rate selection. 7 Field 6 5 4 3 2 — 1 0 IC Reset 0000_0000 R/W Read/Write Address MBAR + 0x284 Figure 8-6. I2C Frequency Divider Register (IFDR) Table 8-3 describes IFDR[IC]. Table 8-3. IFDR Field Descriptions Bits Name 7–6 — Reserved, should be cleared. Description 5–0 IC I2C clock rate. Prescales the clock for bit-rate selection. Due to potentially slow SCL and SDA rise and fall times, bus signals are sampled at the prescaler frequency.
Programming Model Field 7 6 5 4 3 2 IEN IIEN MSTA MTX TXAK RSTA Reset 1 0 — 0000_0000 R/W Read/Write Address MBAR + 0x288 Figure 8-7. I2C Control Register (I2CR) Table 8-4 describes I2CR fields. Table 8-4. I2CR Field Descriptions Bits Name Description 7 IEN I2C enable. Controls the software reset of the entire I2C module.
Programming Model Field 7 6 5 4 3 2 1 0 ICF IAAS IBB IAL — SRW IIF RXAK R/W R Reset R/W 1000_0001 R R R/W Address MBAR + 0x28C Figure 8-8. I2CR Status Register (I2SR) Table 8-5 describes I2SR fields. Table 8-5. I2SR Field Descriptions Bits Name Description 7 ICF Data transferring bit. While one byte of data is transferred, ICF is cleared. 0 Transfer in progress 1 Transfer complete. Set by the falling edge of the ninth clock of a byte transfer.
I2C Programming Examples next byte data receiving. In slave mode, the same function is available after it is addressed. 7 6 5 4 3 Field D Reset 0000_0000 R/W 2 1 0 Read/Write Address MBAR + 0x290 Figure 8-9. I2C Data I/O Register (I2DR) 8.6 I2C Programming Examples The following examples show programming for initialization, signalling START, post-transfer software response, signalling STOP, and generating a repeated START. 8.6.
I2C Programming Examples The free time between a STOP and the next START condition is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the SCL period, it may be necessary to wait until the I2C is busy after writing the calling address to the I2DR before proceeding with the following instructions. The following example signals START and transmits the first byte of data (slave address): CHFLAG MOVE.B I2SR,-(A0);Check I2SR[MBB] BTST.
I2C Programming Examples BEQ.S RECEIVE;Branch if in receive mode MOVE.B I2SR,-(A7);Push the address on stack, BTST.B #0,(A7)+;check ACK from receiver BNE.B END;If no ACK, end of transmission TRANSMITMOVE.B DATABUF,-(A7);Stack data byte MOVE.B (A7)+, I2DR;Transmit next byte of data 8.6.4 Generation of STOP A data transfer ends when the master signals a STOP, which can occur after all data is sent, as in the following example. MASTX END MOVE.B I2SR, -(A7);If no ACK, branch to end BTST.B #0,(A7)+ BNE.
I2C Programming Examples 8.6.6 Slave Mode In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (I2CR[MTX]) according to the I2SR[SRW]. Writing to the I2CR clears the IAAS automatically.
I2C Programming Examples Clear IIF Y TX TX/Rx ? Master Mode? N Y RX Arbitration Lost? N Last Byte Transmitted ? N RXAK= 0 ? Clear IAL Y Last Byte to be Read ? N Y Y N End of ADDR Cycle (Master RX) ? N Write Next Byte to I2DR N Y Y (Read)Y N Data Cycle SRW=1 ? Generate STOP Signal Y Set TX Mode Switch to Rx Mode Generate STOP Signal Tx/Rx ? N (WRITE) N Write Data to I2DR Dummy Read from I2DR IAAS=1 ? Address Y Cycle 2nd Last Byte to be Read? Set TXAK =1 Y IAAS=1 ? Rea
Chapter 9 Interrupt Controller This chapter describes the operation of the interrupt controller portion of the system integration module (SIM). It includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. 9.
Interrupt Controller Registers The SIM provides the following registers for managing interrupts: • • • • • Each potential interrupt source is assigned one of the 10 interrupt control registers (ICR0–ICR9), which are used to prioritize the interrupt sources. The interrupt mask register (IMR) provides bits for masking individual interrupt sources. The interrupt pending register (IPR) provides bits for indicating when an interrupt request is being made (regardless of whether it is masked in the IMR).
Interrupt Controller Registers Table 9-2. Interrupt Control Registers (Continued) MBAR Offset Register Name 0x053 ICR7 DMA1 0x054 ICR8 DMA2 0x055 ICR9 DMA3 Internal interrupts are programmed to a level and priority. Each internal interrupt has a unique ICR. Each of the 7 interrupt levels has 5 priorities, for a total of 35 possible priority levels, encompassing internal and external interrupts.
Interrupt Controller Registers NOTE: Assigning the same interrupt level and priority to multiple ICRs causes unpredictable system behavior. Table 9-4 shows possible priority schemes for internal and external sources of the MCF5407. The internal module interrupt source in this table can be any internal interrupt source programmed to the given level and priority. This table shows how external interrupts are prioritized with respect to internal interrupt sources within the same level.
Interrupt Controller Registers Table 9-4.
Interrupt Controller Registers . Table 9-5. AVR Field Descriptions Bit Name 7–1 AVEC Autovector control. Determines whether the external interrupt at that level is autovectored. 0 Interrupting source returns vector during interrupt-acknowledge cycle. 1 SIM generates autovector during interrupt-acknowledge cycle. 0 BLK Description Block address strobe (AS) for external AVEC access.
Interrupt Controller Registers 31 30 29 28 27 26 25 24 Field — Reset — R/W 23 22 21 20 19 18 17 16 DMA3 DMA2 1 1 Read-only (IPR); R/W (IMR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field DMA1 DMA0 UART1 UART0 I2C TIMER2 TIMER1 SWT EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 Reset 1111 1111 1111 R/W Read-only (IPR); R/W (IMR) Addr MBAR + 0x040 (IPR); + 0x044 (IMR) 1 1 — 1 — Figure 9-4.
Interrupt Controller Registers Table 9-8. IRQPAR Field Descriptions Bits Name Description 7–5 IRQPARn Configures the IRQ pin assignments and priorities IRQPARn External Pin IRQPARn = 0 IRQPARn = 1 IRQPAR2 IRQ5 Level 5 Level 4 IRQPAR1 IRQ3 Level 3 Level 6 IRQPAR0 IRQ1 Level 1 Level 2 4–2 — Reserved, should be cleared. 1–0 ENBDACKn Enable DACK1 and DACK0. Determines the functionality of the respective TMn/DACKn pins. 0 TM1 and TM0 are driven instead of DACK1 and DACK0.
Chapter 10 Chip-Select Module This chapter describes the MCF5407 chip-select module, including the operation and programming model of the chip-select registers, which include the chip-select address, mask, and control registers. 10.
Chip-Select Operation Table 10-2.
Chip-Select Operation • • Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See Section 10.4.1.2, “Chip-Select Mask Registers (CSMR0–CSMR7).” Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, and automatic acknowledge generation features. See Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).
Chip-Select Operation 10.3.1.1 8-, 16-, and 32-Bit Port Sizing Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).” Figure 10-1 shows the correspondence between data byte lanes and the external chip-select memory. Note that all lanes are driven, although unused lines are undefined.
Chip-Select Registers Table 10-5. D[6:5]/PS[1:0], Port Size of Boot CS0 D[6:5]/PS[1:0] Boot CS0 Port Size at Reset 00 32-bit port 01 8-bit port 1x 16-bit port Table 10-6. D3/BE_CONFIG0, BE[3:0] Boot Configuration D3/BE_CONFIG0 Configuration of Byte Enables for Boot CS0 0 BE[3:0] is enabled as byte write enables only. 1 BE[3:0] is enabled as byte enables for reads and writes.
Chip-Select Registers Table 10-7. Chip-Select Registers (Continued) MBAR Offset [31:24] [15:8] [7:0] 0x0B8 Reserved1 Chip-select control register—bank 4 (CSCR4) [p. 10-8] 0x0BC Chip-select address register—bank 5 (CSAR5) [p. 10-6] Reserved1 0x0C0 Chip-select mask register—bank 5 (CSMR5) [p. 10-7] 0x0C4 Reserved Chip-select control register—bank 5 (CSCR5) [p. 10-8] 0x0C8 Chip-select address register—bank 6 (CSAR6) [p. 10-6] Reserved1 0x0CC Chip-select mask register—bank 6 (CSMR6) [p.
Chip-Select Registers Table 10-8. CSARn Field Description Bits Name Description 15–0 BA Base address. Defines the base address for memory dedicated to chip select CS[7:0]. BA is compared to bits 31–16 on the internal address bus to determine if chip-select memory is being accessed. 10.4.1.2 Chip-Select Mask Registers (CSMR0–CSMR7) The chip select mask registers, Figure 10-3, are used to specify the address mask and allowable access types for the respective chip selects. .
Chip-Select Registers Table 10-9. CSMRn Field Descriptions (Continued) Bits Name 5–1 C/I, SC, SD, UC, UD Description Address space mask bits. These bits determine whether the specified accesses can occur to the address space defined by the BAM for this chip select.
Chip-Select Registers Table 10-10. CSCRn Field Descriptions Bits Name Description 8 AA Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by the chip-select address. 0 No internal TA is asserted. Cycle is terminated externally. 1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn and the external system asserts an external TA before the wait-state countdown asserts the internal TA, the cycle is terminated.
Chip-Select Registers CSAR5 EQU MBARx+0x0BC CSMR5 EQU MBARx+0x0C0 CSCR5 EQU MBARx+0x0C6 ;Chip select 5 address register ;Chip select 5 mask register ;Chip select 5 control register CSAR6 EQU MBARx+0x0C8 CSMR6 EQU MBARx+0x0CC CSCR6 EQU MBARx+0x0D2 ;Chip select 6 address register ;Chip select 6 mask register ;Chip select 6 control register CSAR7 EQU MBARx+0x0D4 CSMR7 EQU MBARx+0x0D8 CSCR7 EQU MBARx+0x0DE ;Chip select 7 address register ;Chip select 7 mask register ;Chip select 7 control register ; All o
Chapter 11 Synchronous/Asynchronous DRAM Controller Module This chapter describes configuration and operation of the synchronous/asynchronous DRAM controller component of the system integration module (SIM). It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter consists of the two following parts: • • Section 11.
Overview 11.1.1 Definitions The following terminology is used in this chapter: • • • A/SDRAM block—Any group of DRAM memories selected by one of the MCF5407 RAS[1:0] signals. Thus, the MCF5407 can support two independent memory blocks. The base address of each block is programmed in the DRAM address and control registers (DACR0 and DACR1). SDRAM—RAMs that operate like asynchronous DRAMs but with a synchronous clock, a pipelined, multiple-bank architecture, and faster speed.
DRAM Controller Operation • • • • Control logic and state machine—Generates all DRAM signals, taking bus cycle characteristic data from the block logic, along with hit information to generate DRAM accesses. Handles refresh requests from the refresh counter. — DRAM control register (DCR)—Contains data to control refresh operation of the DRAM controller. Both memory blocks are refreshed concurrently as controlled by DCR[RC].
Asynchronous Operation 11.3 Asynchronous Operation The DRAM controller supports asynchronous DRAMs for cost-effective systems. Typical access times for the DRAM controller interfacing to ADRAM are 4-3-3-3. The DRAM controller supports the following four asynchronous modes: • • • • Non-page mode Burst page mode Continuous page mode Extended data-out mode In asynchronous mode, RAS and CAS always transition at the falling clock edge.
Asynchronous Operation 15 Field SO Reset 14 13 — NAM 12 11 10 RRA 0 9 8 0 RRP RC Uninitialized R/W R/W Address MBAR + 0x100 Figure 11-2. DRAM Control Register (DCR) (Asynchronous Mode) Table 11-3 describes DCR fields. Table 11-3. DCR Field Descriptions (Asynchronous Mode) Bits Name Description 15 SO Synchronous operation. Selects synchronous or asynchronous mode. A DRAM controller in synchronous mode can be switched to ADRAM mode only by resetting the MCF5407.
Asynchronous Operation 31 18 17 16 Field BA Reset — Unitialized 15 14 13 12 11 10 RE — CAS RP 9 RNCN 0 8 7 6 RCD — EDO 5 4 PS 3 2 PM 1 0 — Unitialized R/W R/W Addr MBAR + 0x10C (DACR0); 0x110 (DACR1) Figure 11-3. DRAM Address and Control Registers (DACR0/DACR1) Table 11-4 describes DACRn fields. Table 11-4. DACR0/DACR1 Field Description Bits Name Description 31–18 BA Base address.
Asynchronous Operation Table 11-4. DACR0/DACR1 Field Description (Continued) Bits Name Description 5–4 PS Port size. Determines the port size of the associated DRAM block. For example, if two 16-bit wide DRAM components form one DRAM block, the port size is 32 bits. Programming PS allows the DRAM controller to execute dynamic bus sizing for associated accesses. 00 32-bit port 01 8-bit port 1x 16-bit port 3–2 PM Page mode. Configures page-mode operation for the memory block.
Asynchronous Operation Table 11-5. DMR0/DMR1 Field Descriptions (Continued) Bits Name 6–1 AMx Description Address modifier masks. Determine which accesses can occur in a given DRAM block.
Asynchronous Operation Table 11-6. Generic Address Multiplexing Scheme (Continued) Address Pin Row Address Column Address 20 20 19 21 21 20 22 22 21 23 23 22 24 24 23 25 25 24 Notes Relating to Port Sizes Note the following: • • • • • Each MCF5407 address bit drives both a row address and a column address bit. As the user upgrades ADRAM, corresponding MCF5407 address bits must be connected. This multiplexing scheme allows various memory widths to be connected to the address bus.
Asynchronous Operation Table 11-7.
Asynchronous Operation Table 11-9. DRAM Addressing for 32-Bit Wide Memories MCF5407 Address Pin MCF5407 Address Bit Driven for RAS MCF5407 Address Bit Driven when CAS is Asserted 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 9 9 8 17 17 16 19 19 18 1 Mbyte 21 21 20 4 Mbytes 23 23 22 16 Mbytes 25 25 24 64 Mbytes Memory Size Base Memory Size of 64 Kbytes 256 Kbytes 11.3.3.
Asynchronous Operation Figure 11-6 shows a variation of the basic cycle. In this case, RCD is 1, so there are two clocks between RAS and CAS. Note that the address is multiplexed on the rising clock immediately before CAS is asserted. Because RNCN = 0, RAS and CAS are negated together. The next bus cycle is initiated, but because DACRn[RP] requires RAS to be precharged for two clocks, RAS is delayed for a clock in the bus cycle. Note that this does not delay the address signals, only RAS.
Asynchronous Operation CLKIN A[31:0] Row Column Column Column Column RAS[1] or [0] RCD = 0 CAS[3:0] CAS = 01 DRAMW D[31:0] Figure 11-7. Burst Page-Mode Read Operation (4-3-3-3) Figure 11-8 shows the write operation with the same configuration. CLKIN A[31:0] Row Column Column Column Column RAS[1] or [0] RCD = 0 CAS[3:0] CAS = 01 DRAMW D[31:0] Figure 11-8. Burst Page-Mode Write Operation (4-3-3-3) 11.3.3.
Asynchronous Operation the next bus cycle are often available before the current cycle completes. The two addresses are compared at the end of the cycle to determine if the next address hits the same page. If so, RAS remains asserted. If not, or if no access is pending, RAS is precharged before the next bus cycle is active on the external bus. As a result, a page miss suffers no penalty. Single accesses not followed by a hit in the page look like non-page-mode accesses.
Asynchronous Operation CLKIN A[31:0] Row Column Column Page Hit RAS[1] or [0] Page Miss RCD = 0 CAS[3:0] CAS = 01 DRAMW D[31:0] Bus Cycle 1 Bus Cycle 2 Figure 11-10. Write Hit in Continuous Page Mode 11.3.3.4 Extended Data Out (EDO) Operation EDO is a variation of page mode that allows the DRAM to continue driving data out of the device while CAS is precharging.
Synchronous Operation 11.3.3.5 Refresh Operation The DRAM controller supports CAS-before-RAS refresh operations that are not synchronized to bus activity. A special DRAMW pin is provided so refresh can occur regardless of the state of the processor bus. When the refresh counter rolls over, it sets an internal flag to indicate that a refresh is pending. If that happens during a continuous page-mode access, the page is closed (RAS precharged) when the data transfer completes to allow the refresh to occur.
Synchronous Operation Table 11-10. SDRAM Commands Command Definition ACTV Activate. Executed before READ or WRITE executes; SDRAM registers and decodes row address. MRS Mode register set. NOP No-op. Does not affect SDRAM state machine; DRAM controller control signals negated; RAS asserted. PALL Precharge all. Precharges all internal banks of an SDRAM component; executed before new page is opened. READ Read access. SDRAM registers column address and decodes that a read access is occurring.
Synchronous Operation Table 11-11. Synchronous DRAM Signal Connections (Continued) Signal CLKIN Description Bus clock output. Connects to the CLK input of SDRAMs. EDGESEL Synchronous edge select. Provides additional output hold time for signals that interface to external SDRAMs. EDGESEL supports the three following modes for SDRAM interface signals: • Tied high. Signals change on the rising edge of CLKIN. • Tied low. Signals change on the falling edge of CLKIN. • Tied to buffered CLKIN.
Synchronous Operation CLKIN CLKIN Address/ Data VALID VALID VALID Address/ Data VALID A: Address and Data Timing with EDGESEL Tied High VALID VALID VALID B: Address and Data Timing with EDGESEL Tied Low Buffer Delay CLKIN Buffered CLKIN Address/ Data VALID VALID VALID VALID C: Address and Data Timing with EDGESEL Tied to Buffered Clock Figure 11-14. Using EDGESEL to Change Signal Timing 11.4.
Synchronous Operation Table 11-12. DCR Field Descriptions (Synchronous Mode) (Continued) Bits Name Description 12 COC Command on SDRAM clock enable (SCKE). Implementations that use external multiplexing (NAM = 1) must support command information to be multiplexed onto the SDRAM address bus. 0 SCKE functions as a clock enable; self-refresh is initiated by the DRAM controller through DCR[IS]. 1 SCKE drives command information.
Synchronous Operation Table 11-13 describes DACRn fields. Table 11-13. DACR0/DACR1 Field Descriptions (Synchronous Mode) Bit Name 31–18 BA Base address register. With DCMR[BAM], determines the address range in which the associated DRAM block is located. Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits match, the address hits in the associated DRAM block. BA functions the same as in asynchronous operation. 17–16 — Reserved, should be cleared.
Synchronous Operation Table 11-13. DACR0/DACR1 Field Descriptions (Synchronous Mode) (Continued) Bit Name Description IMRS Initiate mode register set (MRS) command. Setting IMRS generates a MRS command to the associated SDRAMs. In initialization, IMRS should be set only after all DRAM controller registers are initialized and PALL and REFRESH commands have been issued. After IMRS is set, the next access to an SDRAM block programs the SDRAM’s mode register.
Synchronous Operation Table 11-14. DMR0/DMR1 Field Descriptions Bits Name Description 31–18 BAM Base address mask. Masks the associated DACRn[BA]. Lets the DRAM controller connect to various DRAM sizes. Mask bits need not be contiguous (see Section 11.5, “SDRAM Example.”) 0 The associated address bit is used in decoding the DRAM hit to a memory block. 1 The associated address bit is not used in the DRAM hit decode. 17–9 — 8 WP 7 — 6–1 AMx Reserved, should be cleared. Write protect.
Synchronous Operation tables, find the one that corresponds to the number of column address lines on the SDRAM and to the port size as seen by the MCF5407, which is not necessarily the SDRAM port size. For example, if two 1M x 16-bit SDRAMs together form a 2M x 32-bit memory, the port size is 32 bits. Most SDRAMs likely have fewer address lines than are shown in the tables, so follow only the connections shown until all SDRAM address lines are connected. Table 11-15.
Synchronous Operation Table 11-19. MCF5407 to SDRAM Interface (8-Bit Port,13-Column Address Lines) MCF5407 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 16 15 14 13 12 11 10 9 19 21 23 25 0 1 2 3 4 5 6 7 8 18 20 22 24 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Table 11-20.
Synchronous Operation Table 11-24. MCF5407 to SDRAM Interface (16-Bit Port, 12-Column Address Lines) MCF5407 A16 A15 A14 A13 A12 A11 A10 Pins A9 A18 A20 A22 A24 A25 A26 A27 A28 A29 A30 A31 Row 16 15 14 13 12 11 10 9 18 20 22 24 Column 1 2 3 4 5 6 7 8 17 19 21 23 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 25 26 27 28 29 30 31 A10 A11 A12 A13 A14 A15 A16 A17 A18 Table 11-25.
Synchronous Operation Table 11-29. MCF5407 to SDRAM Interface (32-Bit Port, 11-Column Address Lines) MCF5407 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 15 14 13 12 11 10 9 17 19 21 23 Column 2 3 4 5 6 7 8 16 18 20 22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 24 25 26 27 28 29 30 31 Table 11-30.
Synchronous Operation latency (SCAS assertion to data out), this value is also 2 CLKIN cycles. Notice that NOPs are executed until the last data is read. A PALL command is executed one cycle after the last data transfer. CLKIN A[31:0] Row Column Column Column Column SRAS tRCD = 2 SCAS tEP DRAMW tCASL = 2 D[31:0] RAS[0] or [1] CAS[3:0] ACTV NOP READ NOP NOP PALL Figure 11-18. Burst Read SDRAM Access Figure 11-19 shows the burst write operation.
Synchronous Operation CLKIN A[31:0] Row Column Column Column Column SRAS tRP SCAS tCASL = 2 tRWL DRAMW D[31:0] RAS[0] or [1] CAS[3:0] ACTV NOP WRITE NOP PALL Figure 11-19. Burst Write SDRAM Access Accesses in synchronous burst page mode always cause the following sequence: 1. 2. 3. 4. 5. 6. command NOP commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no NOP commands). Required number of READ or WRITE commands to service the transfer size with the given port size.
Synchronous Operation • If the next bus cycle is pending and hits in the page, the page is left open, and the next SDRAM access begins with a READ or WRITE command. Because of the nature of the internal CPU pipeline this condition does not occur often, however, the use of continuous page mode is recommended because it can provide a slight performance increase. Figure 11-20 shows two read accesses in continuous page mode. Note that there is no precharge between the two accesses.
Synchronous Operation CLKIN Row A[31:0] Column Column SRAS SCAS tEP tRCD = 3 DRAMW tCASL = 3 D[31:0] RAS[0] or [1] CAS[3:0] ACTV NOP WRITE NOP READ NOP NOP NOP PALL Figure 11-21. Synchronous, Continuous Page-Mode Access—Read after Write 11.4.4.5 Auto-Refresh Operation The DRAM controller is equipped with a refresh counter and control. This logic is responsible for providing timing and control to refresh the SDRAM.
Synchronous Operation CLKIN A[31:0] SRAS tRC = 6 tRCD = 2 SCAS DRAMW RAS[0] or [1] PALL NOP REF NOP ACTV Figure 11-22. Auto-Refresh Operation 11.4.4.6 Self-Refresh Operation Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at the same time to perform an internal refresh operation and to maintain the integrity of the data stored in the SDRAM. The DRAM controller supports self-refresh with DCR[IS]. When IS is set, the SELF command is sent to the SDRAM.
Synchronous Operation supports this sequence with the following procedure: 1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset before any action is taken on the SDRAMs. This is normally around 100 µs. 2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet enable PALL or REF commands. 3. Issue a PALL command to the SDRAMs by setting DCR[IP] and accessing a SDRAM location. Wait the time (determined by tRP) before any other execution. 4.
SDRAM Example access can be a read or write. The important thing is that the address output of that access needs the correct mode programming information on the correct address bits. Figure 11-24 shows the MRS command, which occurs in the first clock of the bus cycle. CLKIN A[31:0] SRAS, SCAS DRAMW D[31:0] RAS[1] or [0] MRS Figure 11-24. Mode Register Set (MRS) Command 11.5 SDRAM Example This example interfaces a 2M x 32-bit x 4 bank SDRAM component to a MCF5407 operating at 40 MHz.
SDRAM Example Table 11-33. SDRAM Hardware Connections MCF5407 Pins A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 = CMD BA0 BA1 11.5.2 DCR Initialization At power-up, the DCR has the following configuration if synchronous operation and SDRAM address multiplexing is desired. 15 Field SO Setting 1 14 13 res X 0 (hex) 12 NAM COC 0 11 IS 0 10 9 8 0 RTIM 0 8 0 RC 0 0 0 0 1 0 0 2 1 1 0 6 Figure 11-25.
SDRAM Example Accessible Memory SDRAM Component Bank 0 Bank 1 512 Kbyte Bank 2 512 Kbyte 1 Mbyte Bank 3 512 Kbyte 1 Mbyte 512 Kbyte 1 Mbyte 512 Kbyte 1 Mbyte 512 Kbyte 512 Kbyte 512 Kbyte Figure 11-26. SDRAM Configuration The DACRs should be programmed as shown in Figure 11-27.
SDRAM Example Table 11-35. DACR Initialization Values Bits Name Setting 2 PM 1 1–0 — Description Indicates continuous page mode Reserved. Don’t care. 11.5.4 DMR Initialization In this example, again, only the second 512-Kbyte block of each 1-Mbyte space is accessed in each bank. In addition the SDRAM component is mapped only to readable and writable supervisor and user data. The DMRs have the following configuration.
SDRAM Example 11.5.5 Mode Register Initialization When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding MCF5407 address pins must be determined while being aware of masking requirements. Table 11-37 lists the desired initialization setting: Table 11-37.
SDRAM Example 11.5.6 Initialization Code The following assembly code initializes the SDRAM example. Power-Up Sequence: move.w move.w move.l move.l move.l move.l #0x8026, d0 d0, DCR #0xFF880300, d0 d0, DACR0 #0x00740075, d0 d0, DMR0 //Initialize DCR //Initialize DACR0 //Initialize DMR0 Precharge Sequence: move.l move.l move.l move.l #0xFF880308, d0 d0, DACR0 #0xBEADDEED, d0 d0, 0xFF880000 //Set DACR0[IP] //Write to memory location to init. precharge Refresh Sequence: move.l move.
SDRAM Example 11-40 MCF5407 User’s Manual
Part III Peripheral Module Intended Audience Part III describes the operation and configuration of the MCF5407 DMA, timer, UART, and parallel port modules, and describes how they interface with the system integration unit, described in Part II. Contents It contains the following chapters: — Chapter 12, “DMA Controller Module,” provides an overview of the DMA controller module and describes in detail its signals and registers.
Audio CODEC ‘97 Component Specification Acronyms and Abbreviations Table III-i describes acronyms and abbreviations used in Part III. Table III-i.
Table III-i. Acronyms and Abbreviated Terms (Continued) Term Meaning PCLK Processor clock PLL Phase-locked loop PLRU Pseudo least recently used POR Power-on reset PQFP Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Part III.
III-iv MCF5407 User’s Manual
Chapter 12 DMA Controller Module This chapter describes the MCF5407 DMA controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. 12.1 Overview The direct memory access (DMA) controller module provides an efficient way to move blocks of data with minimal processor interaction.
DMA Signal Description 12.1.
DMA Signal Description Table 12-1. DMA Signals (Continued) Signal I/O Description TM[2:0]/ DACK[1:0] O Transfer modifier/DMA acknowledge. The MCF5407 TM[2:0] encodings are like the MCF5307, with functions shifted slightly, as Figure 12-2 shows. Dedicated DMA acknowledgement pins, DACK[1:0], are added and multiplexed as follows—TM[1:0]/DACK[1:0]/PP[3:2]. TM2 is still multiplexed only with PP4. Chapter 17, “Signal Descriptions,” describes multiplexing.
DMA Transfer Overview MCF5307 Function Pin Pin MCF5407 Function Single/dual cycle access TM0 TM0 DMA 0 acknowledge DMA 0 acknowledge configuration TM1 TM1 DMA 1 acknowledge DMA 1 acknowledge configuration TM2 TM2 Single/dual cycle access Figure 12-2. MCF5307/MCF5407 TM[2:0] Pin Remapping 12.3 DMA Transfer Overview The DMA module usually transfers data faster than the ColdFire core can under software control.
DMA Controller Module Programming Model • Single-address transfers—An external device can initiate a single-address transfer by asserting DREQ. The MCF5407 provides address and control signals for single-address transfers. The external device reads to or writes from the specified address, as Figure 12-4 shows. External logic is required. Write: Control Signals Memory DMA Data Control Signals Peripheral Read: Control Signals Memory DMA Data Control Signals Peripheral Figure 12-4.
DMA Controller Module Programming Model Table 12-3. Memory Map for DMA Controller Module Registers DMA Channel MBAR Offset 0 0x300 Source address register 0 (SAR0) [p. 12-7] 0x304 Destination address register 0 (DAR0) [p. 12-7] 0x308 DMA control register 0 (DCR0) [p. 12-8] 1 2 3 [31:24] [23:16] [15:8] 0x30C Reserved Byte count register 0 (BCR0) [p. 12-7] 0x310 DMA status register 0 (DSR0) [p. 12-10] Reserved 0x314 DMA interrupt vector register 0 (DIVR0) [p.
DMA Controller Module Programming Model 12.4.1 Source Address Registers (SAR0–SAR3) SARn, Figure 12-5, contains the address from which the DMA controller requests data. In single-address mode, SARn provides the address regardless of the direction. 31 0 Field SAR Reset 0000_0000_0000_0000_0000_0000_0000_0000 R/W R/W Address MBAR + 0x300, 0x340, 0x380, 0x3C0 Figure 12-5.
DMA Controller Module Programming Model 31 24 23 0 Field — BCR Reset — 0000_0000_0000_0000_0000_0000 R/W R/W Address MBAR + 0x30C, 0x34C, 0x38C, 0x3AC Figure 12-7. Byte Count Registers (BCRn) DSR[DONE], shown in Figure 12-9, is set when the block transfer is complete. When a transfer sequence is initiated and BCRn[BCR] is not divisible by 16, 4, or 2 when the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no transfer occurs. See Section 12.4.
DMA Controller Module Programming Model Table 12-4. DCRn Field Descriptions (Continued) Bits Name Description 29 CS Cycle steal. 0 DMA continuously makes read/write transfers until the BCR decrements to 0. 1 Forces a single read/write transfer per request. The request may be internal by setting the START bit, or external by asserting DREQ. 28 AA Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size.
DMA Controller Module Programming Model Table 12-4. DCRn Field Descriptions (Continued) Bits Name Description 15 AT DMA acknowledge type. Controls whether acknowledge information is provided for the entire transfer or only the final transfer. 0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the result of an external request. 1 Final transfer (when BCR reaches zero).
DMA Controller Module Functional Description Table 12-5. DSRn Field Descriptions (Continued) Bits Name Description 1 BSY Busy 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. 1 BSY is set the first time the channel is enabled after a transfer is initiated. 0 DONE Transactions done. Set when all DMA controller transactions complete normally, as determined by transfer count and error conditions.
DMA Controller Module Functional Description 12.5.1 Transfer Requests (Cycle-Steal and Continuous Modes) The DMA channel supports internal and external requests. A request is issued by setting DCR[START] or by asserting DREQ. Setting DCR[EEXT] enables recognition of external interrupts. Internal interrupts are always recognized. Bus usage is minimized for either internal or external requests by selecting between cycle-steal and continuous modes.
DMA Controller Module Functional Description than zero, another read/write transfer is initiated. If the BCR is a multiple of DCR[BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. If a termination error occurs, DSR[BES,DONE] are set and DMA transactions stop. 12.5.2.2 Single-Address Transfers Single-address transfers consist of one DMA bus cycle, allowing either a read or a write cycle to occur.
DMA Controller Module Functional Description The DAR should contain the destination (write) address. If the transfer is from a peripheral device to memory, or memory to memory, the DAR is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, DAR is loaded with the address of the peripheral data register. This address can be any aligned byte address. DAR is not used in single-address mode.
DMA Controller Module Functional Description 0 1 2 3 4 5 6 7 8 9 10 11 CLKIN DREQ0 TM0/DACK0 TT1 TT0 TS CS TA R/W A[31:0] Read Write Figure 12-11. DREQ Timing Constraints, Dual-Address DMA Transfer Although Figure 12-11 does not show TM0/DACK0 signaling a DMA acknowledgement, this signal can provide an external request acknowledge response, as shown in subsequent diagrams. To initiate a request, DREQ need only be asserted long enough to be sampled on one rising clock edge.
DMA Controller Module Functional Description CLKIN TS AS TIP A[31:0] R/W SIZ[1:0] D[31:0] CSx TA DRAMW Precharge SRAS SCAS RAS[1:0] CAS[3:0] TT[1:0] 0 1 0 1 0 TM2 TM0/DACK0 DREQ0 CPU DMA Read CPU DMA Write CPU Figure 12-12. Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer Figure 12-13 shows a single-address DMA transfer in which the peripheral is reading from memory. Note that TM2 is high, indicating a single-address transfer.
DMA Controller Module Functional Description 0 1 2 3 4 5 6 7 8 9 10 11 CLKIN DREQ0 TM0/DACK0 TS A[31:0], SIZ[1:0] TIP R/W TM2 TT0 TT1 CSx, AS OE, BE/BWE TA D[31:0] Figure 12-13. Single-Address DMA Transfer 12.5.4.2 Auto-Alignment Auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and programmed size. To use this feature, DCR[AA] must be set. The source is auto-aligned if SSIZE indicates a transfer size larger than DSIZE.
DMA Controller Module Functional Description 5. Read byte from 0x00F0—write byte, increment SAR. If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size. 12.5.4.3 Bandwidth Control Bandwidth control makes it possible to force the DMA off the bus to allow access to another device. DCR[BWC] provides seven levels of block transfer sizes.
Chapter 13 Timer Module This chapter describes the configuration and operation of the two general-purpose timer modules (timer 0 and timer 1). It includes programming examples. 13.1 Overview The timer module incorporates two independent, general-purpose 16-bit timers, timer 0 and timer 1. The output of an 8-bit prescaler clocks each timer. There are two sets of registers, one for each timer. The timers can operate from CLKIN or from an external clocking source using one of the TIN signals.
General-Purpose Timer Units 13.1.1 Key Features Each general-purpose 16-bit timer unit has the following features: • • • • • • • Maximum period of 4.97 seconds at 54 MHz 18.5-nS resolution at 54 MHz Programmable sources for the clock input, including external clock Input-capture capability with programmable trigger edge on input pin Output-compare with programmable mode for the output pin Free run and restart modes Maskable interrupts on input capture or reference-compare 13.
General-Purpose Timer Programming Model • • Reference compare—A timer can be configured to count up to a reference value, at which point TERn[REF] is set. If TMRn[ORI] is one, an interrupt is issued. If the free run/restart bit TMRn[FRR] is set, a new count starts. If it is clear, the timer keeps running. Output mode—When a timer reaches the reference value selected by TMRn[OM], it can send an output signal on TOUTn.
General-Purpose Timer Programming Model Table 13-2. TMRn Field Descriptions Bits Name Description 15–8 PS Prescaler value. The prescaler is programmed to divide the clock input (CLKIN/(16 or 1) or clock on TIN) by values from 1 (PS = 0000_0000) to 256 (PS = 1111_1111).
General-Purpose Timer Programming Model clocking source and as an input capture pin. 15 0 Field CAP (16-bit capture counter value) Reset 0000_0000_0000_0000 R/W Read only Address MBAR + 0x148 (TCR0); + 0x188 (TCR1) Figure 13-4. Timer Capture Register (TCR0/TCR1) 13.3.4 Timer Counters (TCN0/TCN1) The current value of the 16-bit, incrementing timer counters (TCN0/TCN1), Figure 13-5, can be read anytime without affecting counting. Writing to TCNn clears it.
Code Example Table 13-3 describes TERn fields. Table 13-3. TERn Field Descriptions Bits Name Description 7–2 — 1 REF Output reference event. The counter has reached the TRRn value. Setting TMRn[ORI] enables the interrupt request caused by this event. Writing a one to REF clears the event condition. 0 CAP Capture event. The counter value has been latched into TCRn. Setting TMRn[CE] enables the interrupt request caused by this event. Writing a 1 to CAP clears the event condition. Reserved 13.
Calculating Time-Out Values move.w TMR0,D0;save the contents of TMR0 while setting bset #0,D0 ;the 0 bit. This enables timer 0 and starts counting move.w D0, TMR0 ;load the value back into the register, setting TMR0[RST] T0_LOOP move.b TER0,D1 ;load TER0 and see if btst #1,D1 ;TER0[REF] has been set beq T0_LOOP addi.l #1,D2;Increment D2 cmp.l #5,D2;Did D2 reach 5? (i.e. timer ref has timed) beq T0_FINISH;If so, end timer0 example. Otherwise jump back. move.
Calculating Time-Out Values Table 13-4. Time-Out Values (in Seconds)—TRR[REF] = 0xFFFF (162-MHz Processor Clock) (Continued) CLK = 10 (÷ 1) TMR[PS] (Dec) CLK = 01 (÷ 16) 54 40.5 32.4 54 CLK = 10 (÷ 1) TMR[PS] (Dec) CLKIN (MHz) 40.5 CLK = 01 (÷ 16) CLKIN (MHz) 32.4 54 40.5 32.4 54 40.5 32.4 6 0.136 0.181 0.227 0.008 0.011 0.014 134 2.621 3.495 4.369 0.164 0.218 0.273 7 0.155 0.207 0.259 0.010 0.013 0.016 135 2.641 3.521 4.401 0.165 0.220 0.275 8 0.175 0.233 0.291 0.011 0.015 0.
Calculating Time-Out Values Table 13-4. Time-Out Values (in Seconds)—TRR[REF] = 0xFFFF (162-MHz Processor Clock) (Continued) CLK = 10 (÷ 1) TMR[PS] (Dec) CLK = 01 (÷ 16) 54 40.5 32.4 54 CLK = 10 (÷ 1) TMR[PS] (Dec) CLKIN (MHz) 40.5 CLK = 01 (÷ 16) CLKIN (MHz) 32.4 54 40.5 32.4 54 40.5 32.4 43 0.854 1.139 1.424 0.053 0.071 0.089 171 3.340 4.453 5.567 0.209 0.278 0.348 44 0.874 1.165 1.456 0.055 0.073 0.091 172 3.359 4.479 5.599 0.210 0.280 0.350 45 0.893 1.191 1.489 0.056 0.074 0.
Calculating Time-Out Values Table 13-4. Time-Out Values (in Seconds)—TRR[REF] = 0xFFFF (162-MHz Processor Clock) (Continued) CLK = 10 (÷ 1) TMR[PS] (Dec) CLK = 01 (÷ 16) 54 40.5 32.4 54 CLK = 10 (÷ 1) TMR[PS] (Dec) CLKIN (MHz) 40.5 CLK = 01 (÷ 16) CLKIN (MHz) 32.4 54 40.5 32.4 54 40.5 32.4 80 1.573 2.097 2.621 0.098 0.131 0.164 208 4.058 5.411 6.764 0.254 0.338 0.423 81 1.592 2.123 2.654 0.100 0.133 0.166 209 4.078 5.437 6.796 0.255 0.340 0.425 82 1.612 2.149 2.686 0.101 0.134 0.
Calculating Time-Out Values Table 13-4. Time-Out Values (in Seconds)—TRR[REF] = 0xFFFF (162-MHz Processor Clock) (Continued) CLK = 10 (÷ 1) TMR[PS] (Dec) CLK = 01 (÷ 16) 54 40.5 32.4 54 CLK = 10 (÷ 1) TMR[PS] (Dec) CLKIN (MHz) 40.5 CLK = 01 (÷ 16) CLKIN (MHz) 32.4 54 40.5 32.4 54 40.5 32.4 117 2.291 3.055 3.819 0.143 0.191 0.239 245 4.777 6.369 7.961 0.299 0.398 0.498 118 2.311 3.081 3.851 0.144 0.193 0.241 246 4.796 6.395 7.994 0.300 0.400 0.500 119 2.330 3.107 3.884 0.146 0.
Calculating Time-Out Values 13-12 MCF5407 User’s Manual
Chapter 14 UART Modules This chapter describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5407 and includes programming examples. All references to UART refer to one of these modules when in UART mode as opposed to modem mode. Particular attention is given to the UART1 implementation of a synchronous interface that provides a controller for an 8- or 16-bit CODEC interface and an audio CODEC ‘97 (AC ’97) digital interface. 14.
Serial Module Overview the channel transmitter serial data output (TxD). See Section 14.5.2.1, “Transmitting in UART Mode.” The receiver converts serial data from the channel receiver serial data input (RxD) to parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers the assembled character onto the bus during read operations. The receiver may be polledor interrupt-driven. See Section 14.5.2.3, “Receiver.
Register Descriptions • • • • • • • • • Each channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode Automatic wake-up mode for multidrop applications Four maskable interrupt conditions UART0 and UART1 have interrupt capability to DMA channels 2 and 3, respectively, when either the RxRDY or FFULL bit is set in the USR.
Register Descriptions Table 14-1. UART Module Programming Model MBAR Offset [31:24] [23:16] [15:8] [7:0] UART0 UART1 0x1C0 0x200 UART mode registers1—(UMR1n) [p. 14-5], (UMR2n) [p. 14-7] Rx FIFO threshold register—(RXLVL) [p. 14-8] (UART1 only) Modem control Tx FIFO threshold register—(MODCTL) register—(TXLVL) [p. [p. 14-9] (UART1 only) 14-10] (UART1 only) 0x1C4 0x204 (Read) UART status registers—(USRn) [p. 14-10] — (Read) Rx samples available register—(RSMP) [p.
Register Descriptions Table 14-1. UART Module Programming Model (Continued) MBAR Offset [31:24] [23:16] UART0 UART1 0x1DC 0x21C 0x1E0– 0x1EC 0x220– Do not access2 0x22C — 0x1F0 0x230 UART interrupt vector register—(UIVRn) [p. 14-20] — 0x1F4 0x234 (Read) UART input port registers—(UIPn) [p. 14-20] — UART divider lower registers—(UDLn) [p. 14-19] [15:8] [7:0] — (Write) Do not access2 — 0x1F8 0x238 (Read) Do not access2 — (Write) UART output port bit set command registers—(UOP1n3) [p.
Register Descriptions Field 7 6 5 RxRTS RxIRQ/FFULL ERR Reset 3 PM 2 1 PT 0 B/C 0000_0000 R/W Address 4 R/W MBAR + 0x1C0 (UART0), 0x200 (UART1). After UMR1n is read or written, the pointer points to UMR2n. Figure 14-2. UART Mode Registers 1 (UMR1n) Table 14-2 describes UMR1n fields. Table 14-2. UMR1n Field Descriptions Name Description 7 Bits RxRTS Receiver request-to-send. Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun.
Register Descriptions 14.3.2 UART Mode Register 2 (UMR2n) UART mode registers 2 (UMR2n) control UART module configuration. UMR2n can be read or written when the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses do not update the pointer. 7 Field 6 CM 5 4 TxRTS TxCTS Reset 0 SB 0000_0000 R/W Address 3 R/W MBAR + 0x1C0, 0x200. After UMR1n is read or written, the pointer points to UMR2n. Figure 14-3.
Register Descriptions Table 14-3. UMR2n Field Descriptions (Continued) Bits Name Description 3–0 SB Stop-bit length control. Selects the length of the stop bit appended to the transmitted character. Stop-bit lengths of 9/16th to 2 bits are programmable for 6–8 bit characters. Lengths of 1 1/16th to 2 bits are programmable for 5-bit characters.
Register Descriptions 14.3.4 Modem Control Register (MODCTL) The modem control register (MODCTL), Figure 14-5, controls whether UART1 is in UART mode or in one of three modem modes. Field 7 6 ACRB AWR 5 4 DSL Reset 3 2 DTS1 SHDIR 1 0 MODE 1000_0000 R/W R/W Address MBAR + 0x202 Figure 14-5. Modem Control Register (MODCTL) Table 14-5 describes MODCTL fields. Table 14-5. Modem Control Register (MODCTL) Field Descriptions Bits Name Description 7 ACRB AC ‘97 cold reset (active low).
Register Descriptions 14.3.5 Tx FIFO Threshold Register (TXLVL) Tx FIFO threshold register (TXLVL) supports only UART1 in both UART and modem modes. TXLVL holds the Tx FIFO threshold, the value at which the Tx FIFO is considered to be empty for purposes of alerting the CPU that the Tx FIFO needs more data/samples. 7 5 4 0 Field — TXLVL Reset — 0_0000 R/W R/W Address MBAR + 0x203 Figure 14-6. Tx FIFO Threshold Register (TXLVL) Table 14-6 describes TXLVL fields. Table 14-6.
Register Descriptions Table 14-7. USRn Field Descriptions Bits Name Description 7 RB Received break. The received break circuit detects breaks that originate in the middle of a received character. However, a break in the middle of a character must persist until the end of the next detected character time. RB is not used (and is always 0) in modem mode. 0 No break was received. 1 An all-zero character of the programmed length was received without a stop bit. RB is valid only when RxRDY = 1.
Register Descriptions Table 14-7. USRn Field Descriptions (Continued) Bits Name Description 1 FFULL FIFO full. UART0: 0 The FIFO is not full but may hold up to two unread characters. 1 A character was received and is waiting in the receiver buffer FIFO. UART1 (in UART or modem modes): 1 Rx FIFO is full, as defined by the RXLVL. FFULL is set as soon as the number of bytes in the Rx FIFO exceeds the RXLVL value, due to the transfer of a sample (1 or 2 bytes) from the Rx shift register to the Rx FIFO.
Register Descriptions 7 5 4 0 Field — RSMP Reset — 0_0000 R/W Read only Address MBAR + 0x206 Figure 14-9. Receive Samples Available Register (RSMP) Table 14-9 describes RSMP fields. Table 14-9. RSMP Field Descriptions Bits Name 7–5 — 4–0 RSMP Description Reserved, should be cleared. Number of bytes in the Rx FIFO. 14.3.9 Transmit Space Available Register (TSPC) The transmit space available register (TSPC), Figure 14-10, shows available bytes in Tx FIFO.
Register Descriptions 7 Field 6 4 — 3 MISC Reset 2 1 TC 0 RC 0000_0000 R/W Write only Address MBAR + 0x1C8, 0x208 Figure 14-11. UART Command Register (UCRn) Table 14-11 describes UCRn fields and commands. Examples in Section 14.5.2, “Transmitter and Receiver Operating Modes,” show how these commands are used. Table 14-11. UCRn Field Descriptions Bits 7 Value Command — — 6–4 Description Reserved, should be cleared. MISC Field (This field selects a single command.
Register Descriptions Table 14-11. UCRn Field Descriptions (Continued) Bits Value Command 3–2 Description TC Field (This field selects a single command) 00 NO ACTION TAKEN Causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled. 01 TRANSMITTER Enables operation of the channel’s transmitter. USRn[TxEMP,TxRDY] are set. If the transmitter is already enabled, this command has no effect.
Register Descriptions 7 0 Field RB Reset 0000_0000 R/W Read only Address MBAR + 0x1CC Figure 14-12. UART Receiver Buffer for UART0 (URB0) Figure 14-13 shows the configuration of URB1. 31 24 Field RB[31:24] Reset 23 16 15 RB[23:16] 8 7 RB[15:8] 0 RB[7:0] 0000_0000_0000_0000_0000_0000_0000_0000 R/W Read only Address MBAR + 0x20C Figure 14-13. UART Receiver Buffer for UART1 (URB1) 14.3.
Register Descriptions mode, in modem mode the Tx FIFO in UART1 can be loaded while the Tx is disabled. For UART1, FIFOs can be accessed as longwords. Figure 14-15 shows the configuration of the UTB1. These bits contain the samples in the transmitter buffer for UART1. 31 24 Field 23 16 TB[31:24] 15 8 TB[23:16] Reset 7 0 TB[15:8] TB[7:0] 0000_0000_0000_0000_0000_0000_0000_0000 R/W Write only Address MBAR + 0x20C Figure 14-15. UART Transmitter Buffer for UART1 (UTB1) 14.3.
Register Descriptions 7 1 Field — Reset 0 IEC 0000_0000 R/W Write only Address MBAR + 0x1D0 (UACR0), 0x210 (UACR1) Figure 14-17. UART Auxiliary Control Register (UACRn) Table 14-13 describes UACRn fields. Table 14-13. UACRn Field Descriptions Bits Name 7–1 — 0 IEC Description Reserved, should be cleared. Input enable control. This bit is not used in modem mode. 0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
Register Descriptions Table 14-14. UISRn/UIMRn Field Descriptions Bits 7 Name Description COS Change-of-state. Not used by UART1 in modem mode. 0 UIPCRn[COS] is not selected. 1 Change-of-state occurred on CTS and was programmed in UACRn[IEC] to cause an interrupt. 6–3 — Reserved, should be cleared. 2 DB Delta break. Not used by UART1 in modem mode. 0 No new break-change condition to report. Section 14.3.10, “UART Command Registers (UCRn),” describes the RESET BREAK-CHANGE INTERRUPT command.
Register Descriptions 14.3.17 UART Interrupt Vector Register (UIVRn) The UIVRn, Figure 14-21, contain the 8-bit internal interrupt vector number (IVR). 7 0 Field IVR Reset 0000_1111 R/W R/W Address MBAR + 0x1F0 (UIVR0), 0x230 (UIVR1) Figure 14-21. UART Interrupt Vector Register (UIVRn) Table 14-15 describes UIVRn fields. Table 14-15. UIVRn Field Descriptions Bits Name Description 7–0 IVR Interrupt vector.
UART Module Signal Definitions 14.3.19 UART Output Port Data Registers (UOP1n/UOP0n) In UART mode, the RTS output can be asserted by writing a 1 to UOP1n[RTS] and negated by writing a 1 to UOP0n[RTS]. UOP registers have no effect in modem mode. See Figure 14-23. 7 1 Field — Reset 0 RTS 0000_0000 R/W Write only Addr UART0: MBAR + 0x1F8 (UOP1), 0x1FC (UOP0); UART1 0x238 (UOP1), 0x23C (UOP0) Figure 14-23. UART Output Port Data 1 Register (UOP1/UOP0) Table 14-17 describes UOP1 fields. Table 14-17.
UART Module Signal Definitions An internal interrupt request signal (IRQ) is provided to notify the interrupt controller of an interrupt condition. The output is the logical NOR of unmasked UISRn bits. The interrupt level of a UART module is programmed in the interrupt controller in the system integration module (SIM). The UART can use the autovector for the programmed interrupt level or supply the vector from the UIVRn when the UART interrupt is acknowledged.
Operation UART RS-232 Transceiver RTS DI2 CTS DO2 TxD DI1 RxD DO1 Figure 14-25. UART/RS-232 Interface Figure 14-26 shows a signal configuration for a UART1/CODEC interface. UART1 MC143416 CODEC TIN1 SSYNC0 CTS SCLK0 TxD SRx0 RxD STx0 Figure 14-26. UART1/CODEC Interface Figure 14-27 shows a signal configuration for a UART1/CODEC interface. An MCF5407 general-purpose I/O (GPIO) is used as a reset to the AC ‘97 device.
Operation 14.5.1.1 Programmable Divider As Figure 14-28 shows, the UART transmitter and receiver can use the following clock sources: • • An external clock signal on the TIN pin that can be divided by 16. When not divided, TIN provides a synchronous clock mode; when divided by 16, it is asynchronous. CLKIN supplies an asynchronous clock source that is divided by 32 and then divided by the 16-bit value programmed in UDUn and UDLn. See Section 14.3.16, “UART Divider Upper/Lower Registers (UDUn/UDLn).
Operation 54MHz Baudrate = -----------------------------------[ 32 × divider ] Let baud rate = 9600; the divider can be calculated as follows: 54MHz Divider = ----------------------------- = 176 ( decimal ) = 0x00B0 [ 32 × 9600 ] Therefore UDUn = 0x00 and UDLn = 0xB0. 14.5.1.2.2 External Clock An external source clock (TIN) can be used as is or divided by 16. Externalclockfrequency Baudrate = --------------------------------------------------------------------16or1 14.5.
Operation 14.5.2.1 Transmitting in UART Mode The transmitter is enabled through the UART command register (UCRn). When it is ready to accept a character, the UART sets USRn[TxRDY]. The transmitter converts parallel data from the CPU to a serial bit stream on TxD. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The lsb is sent first.
Operation C1 in transmission C11 TxD C2 C3 C4 Break C6 Transmitter Enabled USRn[TxRDY] internal module select W2 W W C11 C2 C3 Start break W W W C4 Stop break W W C5 not transmitted C6 CTS3 RTS4 Manually asserted by BIT-SET command Manually asserted 1 Cn = transmit characters 2 W = write 3 UMR2n[TxCTS] = 1 4 UMR2n[TxRTS] = 1 Figure 14-30. Transmitter Timing Diagram 14.5.2.2 Transmitter in Modem Mode (UART1) After a hardware reset, UART1 is in UART mode.
Operation Figure 14-32 is an example timing diagram for the UART1-CODEC interface (msb first). CTS TIN1 Frame Sync TxD D7 D6 D5 D1 D0 RxD D7 D6 D5 D1 D0 Figure 14-32. 8-Bit CODEC Interface Timing (msb First) Figure 14-33 shows an example timing diagram for the UART1-AC ‘97 interface.
Operation 14.5.2.2.1 AC ‘97 Low-Power Mode A general-purpose I/O (GPIO) must be used as an AC ‘97 reset output pin. UART1 monitors the first three time slots of each Tx frame to detect the power-down condition for the AC ‘97 digital interface. The power-down condition is detected as follows: 1. The first 3 bits of slot 1 must be set, indicating that the Tx frame and slots 1 and 2 are valid. 2. Slot 2 holds the address of the power-down register (0x26) in the external AC ‘97 device. 3.
Operation TxD C1 C2 C3 C4 C5 C6 C7 C8 C6, C7, and C8 will be lost Receiver Enabled USRn[RxRDY] USRn[FFULL] internal module select Status Data C5 will be lost (C1) (C2) (C3) (C4) Reset by command Overrun USRn[OE] RTS4 Status Status Status Data Data Data Manually asserted first time, automatically negated if overrun occurs UOP0[RTS] = 1 Automatically asserted when ready to receive Figure 14-34.
Operation The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. If the break begins in the middle of a character, the receiver places the damaged character in the Rx FIFO stack and sets the corresponding USRn error bits and USRn[RxRDY]. Then, if the break lasts until the next character time, the receiver places an all-zero character into the Rx FIFO and sets USRn[RB,RxRDY]. 14.5.2.
Operation 14.5.2.5 FIFO Stack in UART0 The FIFO stack is used in the UART’s receiver buffer logic. The stack consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the RxD (see Figure 14-29). Data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO. Thus, data flowing from the receiver to the CPU is quadruple-buffered.
Operation NOTE: The receiver can still read characters in the FIFO stack if the receiver is disabled. If the receiver is reset, the FIFO stack, RTS control, all receiver status bits, and interrupt requests are reset. No more characters are received until the receiver is reenabled. 14.5.2.6 FIFOs in UART1 For UART1, FIFOs can be accessed as longwords. Other properties are as follows: • • • 8-bit CODEC mode (MODCTL[MODE] = 01): — Can access FIFOs either one, two, or four 1-byte samples at a time.
Operation • For all other modes, the Rx FIFO is effectively 8 x 32. — 8-bit CODEC or as a UART—Rx FIFO holds thirty-two 8-bit samples. One, two, or four bytes/samples can be read from the Rx FIFO per internal bus cycle. — 16-bit CODEC—Rx FIFO holds sixteen 16-bit samples. Either one or two 16-bit samples can be read from the Rx FIFO per internal bus cycle. 14.5.3 Looping Modes The UART can be configured to operate in various looping modes as shown in Figure 14-34 on page 14-30.
Operation Features of this local loop-back mode are as follows: • • • • Transmitter and CPU-to-receiver communications continue normally in this mode. RxD input data is ignored TxD is held marking The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be. 14.5.3.3 Remote Loop-Back Mode In remote loop-back mode, shown in Figure 14-37, the channel automatically transmits received data bit by bit on the TxD output.
Operation Functional timing information for multidrop mode is shown in Figure 14-38. Master Station A/D TxD ADD1 1 A/D A/D C0 ADD2 1 Transmitter Enabled USRn[TxRDY] internal module select UMR1n[PM] = 11 UMR1n[PT] = 1 ADD 1 C0 UMR1n[PT] = 0 ADD 2 UMR1n[PT] = 2 Peripheral Station RxD A/D A/D 0 ADD1 1 A/D C0 A/D A/D ADD2 1 0 Receiver Enabled USRn[RxRDY] internal module select UMR1n[PM] = 11 UMR1n[PM] = 11 ADD 1 Status Data (C0) Status Data (ADD 2) Figure 14-38.
Operation detection, if 8-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. 14.5.5 Bus Operation This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART module. 14.5.5.1 Read Cycles The UART module responds to reads with byte data. Reserved registers return zeros. 14.5.5.2 Write Cycles The UART module accepts write data as bytes.
Operation • Interrupt handling—Consists of SIRQ (sheet 4), which is executed after the UART module generates an interrupt caused by a change-in-break (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 14.5.6.
Operation ENABLE ENABLA SERIAL MODULE SINIT ANY ERRORS ? INITIATE: Y N CHANNEL INTERRUPTS ENABLE RECEIVER CHK1 CALL CHCHK SAVE CHANNEL STATUS ASSERT REQUEST TO SEND SINITR RETURN Figure 14-39. UART Mode Programming Flowchart (Sheet 1 of 5) Chapter 14.
Operation CHCHK CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE TRANSMITTER CLEAR STATUS WORD TxCHK N IS TRANSMITTER READY ? N Y WAITED TOO LONG ? Y SET TRANSMITTERNEVER-READY FLAG Y SET RECEIVERNEVER-READY FLAG N Y SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK N HAS CHARACTER BEEN RECEIVED ? N WAITED TOO LONG ? Y A B Figure 14-39.
Operation B A FRCHK RSTCHN HAVE FRAMING ERROR ? N Y DISABLE TRANSMITTER RESTORE TO ORIGINAL MODE SET FRAMING ERROR FLAG PRCHK RETURN HAVE PARITY ERROR ? N Y SET PARITY ERROR FLAG A CHRCHK GET CHARACTER FROM RECEIVER SAME AS TRANSMITTED CHARACTER ? Y N SET INCORRECT CHARACTER FLAG B Figure 14-39. UART Mode Programming Flowchart (Sheet 3 of 5) Chapter 14.
Operation INCH SIRQ ABRKI WAS IRQ CAUSED BY BEGINNING OF A BREAK ? Y N DOES CHANNEL A RECEIVER HAVE A CHARACTER ? N Y PLACE CHARACTER IN D0 CLEAR CHANGE-INBREAK STATUS BIT ABRKI1 HAS END-OF-BREAK IRQ ARRIVED YET ? RETURN N Y CLEAR CHANGE-INBREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR RTE Figure 14-39.
Operation OUTCH IS TRANSMITTER READY ? N Y SEND CHARACTER TO TRANSMITTER RETURN Figure 14-39. UART Mode Programming Flowchart (Sheet 5 of 5) Chapter 14.
Operation 14-44 MCF5407 User’s Manual
Chapter 15 Parallel Port (General-Purpose I/O) This chapter describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. It includes a code example for setting up the parallel port. 15.1 Parallel Port Operation The MCF5407 parallel port module has 16 signals, which are programmed as follows: • • • The pin assignment register (PAR) selects the function of the 16 multiplexed pins.
Parallel Port Operation Table 15-1. Parallel Port Pin Descriptions Pin Description PP[15:8]/ A[31:24] MSB of the address bus/parallel port. Programmed through PAR[15–8]. If a PAR bit is 0, the associated pin functions as a parallel port signal. If a bit is 1, the pin functions as an address bus signal. If all pins are address signals, as much as 4 Gbytes of memory space are available. TIP/PP7 Transfer-in-progress output/parallel port bit 7. Programmed through PAR[7].
Parallel Port Operation • • PADAT settings do not affect inputs. PADAT bit values determine the corresponding logic levels of pins configured as outputs. PADAT can be written to anytime. A read from PADAT returns values of corresponding pins configured as general-purpose I/O in the PAR and designated as inputs by the PADDR. 15 0 Field PADAT Reset 0000_0000_0000_0000 R/W R/W Address Address MBAR+0x248 Figure 15-3.
Parallel Port Operation 15.1.4 Code Example The following code example shows how to set up the parallel port. Here, PP[7:0] are general-purpose I/O, PP[3:0] are inputs, and PP[7:4] are outputs. 15-4 MBARx PAR PADDR PADAT EQU EQU EQU EQU 0x00010000 MBARx+0x004 MBARx+0x244 MBARx+0x248 move.l movec move.w move.w move.w move.w move.b move.
Part IV Hardware Interface Intended Audience Part IV is intended for hardware designers who need to know the functions and electrical characteristics of the MCF5407 interface. It includes a pinout, and both electrical and functional descriptions of the MCF5407 signals. It also describes how these signals interact to support the variety of bus operations shown in timing diagrams.
Suggested Reading The following literature may be helpful with respect to the topics in Part IV: • • IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Supplement to Standard Test Access Port and Boundary-Scan Architecture (1149.1) Acronyms and Abbreviations Table IV-i describes acronyms and abbreviations used in Part IV. Table IV-i.
Table IV-i. Acronyms and Abbreviated Terms (Continued) Term Meaning RISC Reduced instruction set computing Rx Receive SIM System integration module TAP Test access port TTL Transistor-to-transistor logic Tx Transmit Part IV.
IV-iv MCF5407 User’s Manual
Chapter 16 Mechanical Data This chapter provides a function pin listing and package diagram for the MCF5407. See the website [http://www.motorola.com/coldfire] for any updated information. 16.1 Package The MCF5407 is assembled in a 208-pin, thermally enhanced plastic QFP package. 16.2 Pinout The MCF5407 pinout is detailed in the following tables, including the primary and secondary functions of multiplexed signals.
Pinout Table 16-1. Pins 1–52 (Left, Top-to-Bottom) (Continued) Pin No 16-2 Name Alternate Function I/O Description Drive (mA) 12 A7 — I/O Address bus bit 8 13 EVCC — — 3.3-V power input — 14 A8 — I/O Address bus bit 8 15 A9 — I/O Address bus bit 8 16 A10 — I/O Address bus bit 8 17 GND — — Ground pin — 18 A11 — I/O Address bus bit 8 19 A12 — I/O Address bus bit 8 20 A13 — I/O Address bus bit 8 21 EVCC — — 3.
Pinout Table 16-1. Pins 1–52 (Left, Top-to-Bottom) (Continued) Pin No Name Alternate Function I/O Description Drive (mA) 47 SIZ1 — I/O Size attribute 8 48 GND — — Ground pin — 49 OE — O Output enable for chip selects 8 50 CS0 — O Chip select 8 51 CS1 — O Chip select 8 52 EVCC — — 3.3-V power input — Table 16-2.
Pinout Table 16-2. Pins 53–104 (Bottom, Left-to-Right) (Continued) Pin No 1 16-4 Name Alternate Function I/O Description Drive (mA) 77 GND — — Ground pin — 78 TOUT1 — O Timer output 8 79 TOUT0 — O Timer output 8 80 TIN0 — I Timer input — 81 EVCC — — 3.
Pinout Table 16-3. Pins 105–156 (Right, Bottom-to-Top) Pin No Name 105 IVCC Alternate Function I/O — — Description 1.8-V power input Drive (mA) — 106 D31 — I/O Data bus 8 107 D30 — I/O Data bus 8 108 D29 — I/O Data bus 8 109 GND — — Ground pin — 110 D28 — I/O Data bus 8 111 D27 — I/O Data bus 8 112 D26 — I/O Data bus 8 113 EVCC — — 3.
Pinout Table 16-3. Pins 105–156 (Right, Bottom-to-Top) (Continued) Pin No Name Alternate Function I/O Description Drive (mA) 139 D6 CS_CONF1 I/O Data bus/Chip select configuration 8 140 D5 CS_CONF0 I/O Data bus/Chip select configuration 8 141 GND — — Ground pin — 142 D4 ADDR_CONF I/O Data bus/Address configuration 8 143 D3 BE_CONFIG0 I/O Data bus/Byte enable configuration 8 144 D2 DIVIDE2 I/O Data bus/Divide control PCLK:CLKIN 8 145 EVCC — — 3.
Pinout Table 16-4. Pins 157–208 (Top, Right-to-Left) (Continued) Pin Alternate Function I/O No Name 168 EDGESEL — I 169 GND — — Description Drive (mA) SDRAM bus clock edge select — Ground pin — 170 BCLKO — O Bus clock output 16 171 IVCC — — 1.8-V power input — 172 RSTO — O Processor reset output 8 173 GND — — Ground pin — 174 CLKIN — I Clock input — 175 IVCC — — 1.
Mechanical Diagram Table 16-4. Pins 157–208 (Top, Right-to-Left) (Continued) Pin 1 Alternate Function I/O PP3 TM1/DACK11 I/O Parallel port bit/Transfer modifier/DMA acknowledge 8 204 PP2 TM0/DACK01 I/O Parallel port bit/Transfer modifier/DMA acknowledge 8 205 EVCC — — 3.
GND PP0 PP1 EVCC PP2 PP3 PP4 GND PP5 PP6 PP7 IVCC PSTDDATA7 PSTDDATA6 GND PSTDDATA5 PSTDDATA4 EVCC PSTDDATA3 PSTDDATA2 GND PSTDDATA1 PSTDDATA0 IVCC PSTCLK GND MTMOD3 MTMOD2 PVCC NC PGND MTMOD1 MTMOD0 IVCC CLKIN GND RSTO IVCC BCLKO GND EDGESEL EVCC TXD0 RXD0 RTS0 CTS0 GND TXD1 RXD1 RTS1 CTS1 IVCC Case Drawing 156 160 165 170 175 180 185 190 205 1 IVCC A0 A1 GND A2 A3 EVCC A4 A5 GND A6 A7 EVCC A8 A9 A10 GND A11 A12 A13 EVCC A14 A15 A16 GND A17 A18 A19 EVCC A20 A21 A22 GND A23 PP8 PP9 EVCC PP10 PP11
Case Drawing Figure 16-2.
Case Drawing View A: Three Places Section A-A: 160 Places Rotated 90° CW View B Figure 16-3. Case Drawing (Details) The dimensions in Figure 16-2 and Figure 16-3 are referenced in Table 16-5. Table 16-5. Dimensions Dimension (Millimeters) Reference Minimum Maximum A — 4.10 A1 0.25 0.50 A2 3.20 3.60 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 D 30.60 BSC Chapter 16.
Case Drawing Table 16-5. Dimensions (Continued) Dimension (Millimeters) Reference Minimum D1 28.00 BSC e 0.50 BSC E 30.60 BSC E1 28.00 BSC L 0.45 L1 R1 16-12 Maximum 0.75 1.30 REF 0.08 — R2 0.08 0.25 S 0.
Chapter 17 Signal Descriptions This chapter describes MCF5407 signals. It includes an alphabetical listing of signals, showing multiplexing, whether it is an input or output to the MCF5407, the state at reset, and whether a pull-up resistor should be used. The following chapter, Chapter 18, “Bus Operation,” describes how these signals interact. NOTE: The terms ‘assertion’ and ‘negation’ are used to avoid confusion when dealing with a mixture of active-low and active-high signals.
Overview ColdFire V4 Core 2 2 Bus Interface Test Controller Debug Module PSTDDATA[7:0] 2 2-Kbyte SRAMs 32 DIV External to Internal Bus 8 2 8 4 Chip Selects 8 MAC 8-Kbyte 16-Kbyte D-Cache I-Cache Parallel Port1 Internal Bus Arbiter Interrupt Controller 1 Parallel 2 I2C port pins (PPn) are multiplexed with other bus functions as shown. is a Philips proprietary interface. Figure 17-1. MCF5407 Block Diagram with Signal Interfaces Table 17-1 lists the MCF5407 signals grouped by functionality.
Overview Table 17-1. MCF5407 Signal Index Signal Name Abbreviation Function I/O Reset Pull-Up Page 17-7 Section 17.2, “MCF5407 Bus Signals” Address A[31:0] 32-bit address bus. A[4:2] indicate the interrupt level for external interrupts. I/O Three state 17-7 Data D[31:0] Data bus. D[7:0] are loaded at reset for bus configuration.
Overview Table 17-1. MCF5407 Signal Index (Continued) Signal Name Address configuration Abbreviation 2 Function I/O Reset Pull-Up Page ADDR_CONFIG Programs parallel I/O ports I — User cfg 17-15 BE[3:0] configuration BE_CONFIG Programs byte enable pins I — User cfg 17-15 Divide control PCLK to CLKIN 2 DIVIDE[2:0] Selects CLKIN/PCLK ratio I — User cfg 17-15 17-15 Section 17.
Overview Table 17-1. MCF5407 Signal Index (Continued) Signal Name Timer outputs Abbreviation TOUT[1:0] Function Outputs waveform or pulse. I/O Reset O High Pull-Up Page 17-19 17-19 Section 17.11, “Parallel I/O Port (PP[15:0])” Parallel port PP[15:0] Interfaces with I/O; multiplexed with bus address and attribute signals. I/O Input 17-19 Section 17.
Overview Table 17-2.
MCF5407 Bus Signals Table 17-2.
MCF5407 Bus Signals • • A[31:24]—Pins are configured as address bits by setting corresponding PAR bits; they represent the most-significant address bus bits. As much as 4 Gbytes of memory are available when all of these pins are programmed as address signals. PP[15:8]—Pins are configured as parallel port signals by clearing corresponding PAR bits; these represent the most-significant parallel port bits. 17.2.2 Data Bus (D[31:0]) The data bus is bidirectional and non-multiplexed.
MCF5407 Bus Signals if a longword access occurs at a misaligned offset of 0x1, a byte is transferred first (SIZ[1:0] = 01), a word is next transferred at offset 0x2 (SIZ[1:0] = 10), then the final byte is transferred at offset 0x4 (SIZ[1:0] = 01). For aligned transfers larger than the port size, SIZ[1:0] behaves as follows: • • If bursting is used, SIZ[1:0] stays at the size of transfer. If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows the port size. Table 17-4.
MCF5407 Bus Signals external master access. This condition is indicated by the AM bit in the chip-select mask register (CSMR) being cleared. See Chapter 10, “Chip-Select Module.” 17.2.8 Transfer In Progress (TIP/PP7) The TIP/PP7 pin is programmed in the PAR to serve as the transfer-in-progress output or as a parallel port bits. The TIP output is asserted indicating a bus transfer is in progress. It is negated during idle bus cycles if the bus is still granted to the processor.
MCF5407 Bus Signals Table 17-6. TM[2:0] Encodings for TT = 00 (Normal Access) (Continued) TM[2:0] Transfer Modifier 110 Supervisor code access 111 Reserved As shown in Table 17-7, if the DMA is bus master (TT = 01), TM[2:0] indicate the type of DMA access and provide the DMA acknowledgement information for channels 0 and 1. In addition, TM[1:0] are multiplexed with DMA acknowledge signals for channels 0 and 1. NOTE: When TT= 01, the TM2 encoding is independent from TM[1:0] encoding. Table 17-7.
Interrupt Control Signals Table 17-10. TM[2:0] Encodings for TT = 11 (Interrupt Level) TM[2:0] Transfer Modifier 000 CPU Space 001 Interrupt level 1 acknowledge 010 Interrupt level 2 acknowledge 011 Interrupt level 3 acknowledge 100 Interrupt level 4 acknowledge 101 Interrupt level 5 acknowledge 110 Interrupt level 6 acknowledge 111 Interrupt level 7 acknowledge 17.3 Interrupt Control Signals The interrupt control signals supply the external interrupt level to the MCF5407 device. 17.3.
Clock and Reset Signals 17.4.3 Bus Driven (BD) The MCF5407 asserts BD to indicate that it is the current master and is driving the bus. The MCF5407 behaves as follows: • • • • If the MCF5407 is the bus master but is not using the bus, BD is asserted. If the MCF5407 loses mastership during a transfer, it completes the last transfer of the access, negates BD, and three-states all bus signals on the rising edge of CLKIN.
Clock and Reset Signals 17.5.5 Data/Configuration Pins (D[7:0]) This section describes data pins, D[7:0], that are read at reset for configuration. Table 17-11 shows pin assignments. Table 17-11. Data Pin Configuration Pin Function D7 Auto-acknowledge configuration (AA_CONFIG) D[6:5] Port size configuration (PS_CONFIG[1:0]) D4 Address configuration (ADDR_CONFIG/D4) D3 Byte enable configuration (BE_CONFIG) D[2:0] Divide control (DIVIDE[2:0]) 17.5.5.
Chip-Select Module Signals 17.5.5.4 D3—Byte-Enable Configuration (BE_CONFIG) The default byte-enable mode of the boot CS0 is determined by the logic level driven on D3 at the rising edge of RSTI. This logic level is reflected as the reset value of CSCR0[BEM]. Table 17-13 shows how the logic levels of D[6:5] correspond to the port size for CS0 at reset. Table 17-14. D3/BE_CONFIG, BE[3:0] Boot Configuration D3 (CSCR0[BEM]) Boot CS0 Byte Enable Configuration 0 Neither BE nor BWE is asserted for read.
DRAM Controller Signals ROM to be selected at any defined address space. Port size and termination (internal vs. external) for boot CS0 are configured by the levels on D[7:5,3] on the rising edge of RSTI, as described in Section 17.5.5.1, “D[7:5,3]—Boot Chip-Select (CS0) Configuration.” The chip-select implementation is described in Chapter 10, “Chip-Select Module.” 17.6.2 Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) The four byte enables are multiplexed with the MCF5407 byte-write-enable signals.
DMA Controller Module Signals 17.7.4 Synchronous DRAM Column Address Strobe (SCAS) The synchronous DRAM column address strobe (SCAS) is registered during synchronous mode to route directly to the SCAS signal of SDRAMs. 17.7.5 Synchronous DRAM Row Address Strobe (SRAS) The synchronous DRAM row address strobe output (SRAS) is registered during synchronous mode to route directly to the SRAS signal of external SDRAMs. 17.7.
Serial Module Signals 17.8.2 Transfer Modifier/DMA Acknowledge (TM[2:0]/DACK[1:0]) Although the MCF5407 provides similar encodings on TM[2:0], DMA acknowledgement pins (DACK[1:0]) are now combined with PP[3:2]/TM[1:0], resulting in three-to-one multiplexed signals, PP[3:2]/TM[1:0]/DACK[1:0]. TM2 is still multiplexed only with PP4. When properly connected, TM[2:0] can be used in MCF5407 designs as on MCF5307 designs, or DACK[1:0] can be used for DMA transfers, as shown in Figure 17-2.
Timer Module Signals 17.9.2 Receiver Serial Data Input (RxD) Data received on RxD is sampled on the rising edge of the clock source, with the lsb received first. For UART1 in modem mode, data received on RxD is sampled on the falling edge of the clock signal driving UART1’s CTS input. UART1 transfers can be specified as either lsb or msb first. 17.9.3 Clear to Send (CTS) This input can generate an interrupt on a change of state.
I2C Module Signals Motorola recommends that D4 be driven during reset to a logic level. 17.12 I2C Module Signals The I2C module acts as a two-wire, bidirectional serial interface between the MCF5407 and peripherals with an I2C interface (such as LED controller, A-to-D converter, or D-to-A converter). Devices connected to the I2C must have open-drain or open-collector outputs. 17.12.
Debug Module/JTAG Signals 17.13.4 Processor Status Debug Data (PSTDDATA[7:0]) Processor status data outputs indicate both processor status and captured address and data values. They operate at half the processor’s frequency, using PSTCLK. Given that real-time trace information appears as a sequence of 4-bit data values, there are no alignment restrictions; that is, PST values and operands may appear on either PSTDDATA[7:0] nibble. The upper nibble, PSTDDATA[7:4], is most significant.
Debug Module/JTAG Signals processor in debug mode. See Chapter 5, “Debug Support.” 17.14.3 Test Data Input/Development Serial Input (TDI/DSI) If MTMOD0 is high, TDI is selected. TDI provides the serial data port for loading the various JTAG boundary scan, bypass, and instruction registers. Shifting in data depends on the state of the JTAG controller state machine and the instruction in the instruction register. Shifts occur on the TCK rising edge.
Chapter 18 Bus Operation This chapter describes data-transfer operations, error conditions, bus arbitration, and reset operations. It describes transfers initiated by the MCF5407 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,” describes DRAM cycles. 18.
Bus Characteristics Table 18-1.
Data Transfer Operation • • • • • Address bus (A[31:0]) Data bus (D[31:0]) Control signals (TS and TA) AS, CSx, OE, BE/BWE Attribute signals (R/W, SIZ, TT, TM, and TIP) The address bus, write data, TS, and all attribute signals change on the rising edge of CLKIN. Read data is latched into the MCF5407 on the rising edge of CLKIN. AS, CSx, OE, and BE/BWE change on the falling edge. The MCF5407 bus supports byte, word, and longword operand transfers and allows accesses to 8-, 16-, and 32-bit data ports.
Data Transfer Operation BE1 BE2 BE3 D[31:24] D[23:16] D[15:8] D[7:0] 32-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 16-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 Byte Enable Processor External Data Bus 8-Bit Port Memory BE0 Driven with indeterminate values Byte 0 Byte 1 Byte 2 Driven with indeterminate values Byte 3 Figure 18-2.
Data Transfer Operation Table 18-3 shows the type of access as a function of match in the CSCRs and DACRs. Table 18-3. Accesses by Matches in CSCRs and DACRs Number of CSCR Matches Number of DACR Matches Type of Access 0 0 External Defined by CSCRs 1 0 Multiple 0 External, burst-inhibited, 32-bit 0 1 Defined by DACRs 1 1 Undefined Multiple 1 Undefined 0 Multiple Undefined 1 Multiple Undefined Multiple Multiple Undefined Basic bus operations occur in three clocks, as follows: 1.
Data Transfer Operation Next Cycle S0 S5 S1 Basic Read/Write Fast Termination S4 S2 Wait States S3 Figure 18-4. Data Transfer State Transition Diagram Table 18-4 describes the states as they appear in subsequent timing diagrams. Note that the TT[1:0], TM[2:0], and TIP functions are chosen in the PAR, as described in Section 15.1.1, “Pin Assignment Register (PAR).” Table 18-4. Bus Cycle States State Cycle CLKIN Description S0 All High The read or write cycle is initiated.
Data Transfer Operation Table 18-4. Bus Cycle States (Continued) State S5 Cycle CLKIN S5 Low Description AS, CS, BE/BWE, and OE are negated on the CLKIN falling edge. The MCF5407 stops driving address lines and R/W on the rising edge of CLKIN, terminating the read or write cycle. At the same time, the MCF5407 negates TT[1:0], TM[2:0], TIP, and SIZ[1:0] on the rising edge of CLKIN.
Data Transfer Operation termination. TA assertion should look the same in either case. S0 S1 S2 S3 S4 S5 CLKIN R/W TT[1:0], TM[2:0] SIZ[1:0], A[31:0] TIP TS AS, CSx BEx, OE Read D[31:0] TA Figure 18-6. Basic Read Bus Cycle Note the following characteristics of a basic read: • • • In S3, data is made available by the external device on the falling edge of CLKIN and is sampled on the rising edge of CLKIN with TA asserted.
Data Transfer Operation System MCF5407 1. Set R/W to write 2. Place address on A[31:0] 3. Assert TT[1:0], TM[2:0], TIP, and SIZ[1:0] 4. Assert TS 5. Assert AS 6. Place data on D[31:0] 7. Negate TS 1. Sample TA low 1. Tree-state D[31:0] 2. Start next cycle 1. Decode address 2. Store data on D[31:0] 3. Assert TA 1. Negate TA Figure 18-7. Write Cycle Flowchart The write cycle timing diagram is shown in Figure 18-8.
Data Transfer Operation S0 S1 S4 S5 CLKIN A[31:0],TT[1:0] TM[2:0, SIZ[1:0]] R/W TIP TS AS, CSx BEx, OE Read D[31:0] TA Figure 18-9. Read Cycle with Fast Termination Figure 18-10 shows a write cycle with fast termination. S0 S1 S4 S5 CLKIN A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BWEx, OE D[31:0] Write TA Figure 18-10. Write Cycle with Fast Termination 18.4.6 Back-to-Back Bus Cycles The MCF5407 runs back-to-back bus cycles whenever possible.
Data Transfer Operation S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 CLKIN A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BE/BWEx OE Read D[31:0] Write TA Figure 18-11. Back-to-Back Bus Cycles Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to the type of operations to be placed back to back. The initiation of a back-to-back cycle is not user definable. 18.4.
Data Transfer Operation 18.4.7.1 Line Transfers A line is a 16-byte-aligned, 16-byte value. Despite the alignment, a line access may not begin on the aligned address; therefore, the bus interface supports line transfers on multiple address boundaries. Table 18-5 shows allowable patterns for line accesses. Table 18-5. Allowable Line Access Patterns A[3:2] Longword Accesses 00 0–4–8–C 01 4–8–C–0 10 8–C–0–4 11 C–0–4–8 18.4.7.2 Line Read Bus Cycles Figure 18-12 shows line read with zero wait states.
Data Transfer Operation S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 CLKIN A[31:0] TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BE/BWEx, OE Read D[31:0] Read Read Read TA Figure 18-13. Line Read Burst (2-1-1-1), Internal Termination Figure 18-14 shows a line access read with one wait state programmed in CSCRx to give the peripheral or memory more time to return read data. This figure follows the same execution as a zero-wait state read burst with the exception of an added wait state. .
Data Transfer Operation S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 A[3:2] = 10 A[3:2] = 11 S6 S7 CLKIN A[3:2] = 00 A[31:0] A[3:2] = 01 R/W TT[1:0] TM[2:0] TIP SIZ[1:0] Line Longword TS AS, CSx BE/BWEx, OE D[31:0] Read Read Read Read Fast Fast Fast TA Basic Figure 18-15. Line Read Burst-Inhibited, Fast, External Termination 18.4.7.3 Line Write Bus Cycles Figure 18-16 shows a line access write with zero wait states.
Data Transfer Operation Figure 18-17 shows a line burst write with one wait-state insertion. S0 S1 S2 S3 WS S4 S5 WS S6 S7 WS S8 S9 WS S10S11 CLKIN A[31:0] R/W, TIP TM[2:0], TT[1:0] SIZ[1:0] TS AS, CSx OE, BWE Write D[31:0] Write Write Write TA Figure 18-17. Line Write Burst (3-2-2-2) with One Wait State, Internal Termination Figure 18-18 shows a burst-inhibited line write. The external device executes a basic write cycle while determining that a line is being transferred.
Misaligned Operands transfer. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 CLKIN A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BE/BWEx, OE Read Read D[31:0] Read Read TA Figure 18-19. Longword Read from an 8-Bit Port, External Termination Note that with external termination, address signals do not change. With internal termination, Figure 18-20, A[1:0] increment for the same longword transfer.
Bus Errors Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch a misaligned instruction word causes an address error exception. The MCF5407 converts misaligned, cache-inhibited operand accesses to multiple aligned accesses. Figure 18-21 shows the transfer of a longword operand from a byte address to a 32-bit port. In this example, SIZ[1:0] specify a byte transfer and a byte offset of 0x1.
Interrupt Exceptions The MCF5407 has the following two levels of interrupt masking: • • Interrupt mask registers in the SIM compare interrupt inputs with programmable interrupt mask levels. The SIM outputs only unmasked interrupts. The status register uses a 3-bit interrupt priority mask. The core recognizes only interrupt requests of higher priority than the value in the mask. See Section 2.2.2.1, “Status Register (SR).
Interrupt Exceptions • • The interrupt request on the interrupt control pins is raised to level 7 and stays there until an interrupt-acknowledge cycle begins. The level later drops but then returns to level 7, causing a second transition on the interrupt control lines. The interrupt request on the interrupt control pins is raised to level 7 and stays there. If the level 7 interrupt routine lowers the mask level, a second level 7 interrupt is recognized without a transition of the interrupt control pins.
Bus Arbitration MCF5407 SYSTEM 1. Drive 0x7FFFFF on A[31:5] 2. Drive 0x0 on A[1:0] 3. Drive interrupt level on A[4:2] 4. Drive R/W to read (R/W = 1) 5. Drive SIZ[1:0] to indicate byte (SIZ[1:0] = 01) 6. Drive TT[1:0] and TM[2:0] to indicate interrupt acknowledge (TT[1:0] = 11; TM[2:0] = interrupt level) 7. Assert TS for one CLKIN cycle 1. Negate TS 2. Drive TM[2:0] to indicate interrupt acknowledge (TM[2:0] = interrupt level) 1. Decode address and select the appropriate slave device.
General Operation of External Master Transfers Table 18-6. MCF5407 Arbitration Protocol States (Continued) State Master Bus Explicit master MCF5407 External master External BD Description Driven Asserted The MCF5407 is explicit bus master when BG is asserted and at least one bus cycle has been initiated. It asserts BD and retains explicit mastership until BG is negated even if no active bus cycles are executed.
General Operation of External Master Transfers • For the MCF5407 to assert a CSx during external master accesses, CSMRn[AM] must be set. External master hits use the corresponding CSCRn settings for auto-acknowledge, byte enables, and wait states. See Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).” To enable DRAM control signals during external master accesses, DCMRn[AM] must be set. During external master bus cycles, either TS or AS (but not both) should be driven to the MCF5407.
General Operation of External Master Transfers NOTE: Bus timing diagrams for external master transfers are not valid for on-chip internal four-channel DMA accesses on the MCF5407. Timing diagrams describe transactions in general terms of bus cycles (Cn) rather than the states (Sn) used in the bus diagrams. Table 18-8 defines the cycles for Figure 18-24. Table 18-8.
General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 CLKIN A[31:0] R/W TT[1:0], TM[2:0] SIZ[1:0] TIP TS AS, BR 2 CS 1 BE/BWE 1 D[31:0] TA 1 BG, BD 2 HOLDREQ External Master 1 Depending on programming, these signals may or may not be driven by the 2 These signals are driven by the processor for an external master transfer. processor. Figure 18-25. External Master Burst Line Access to 32-Bit Port Table 18-9 defines the cycles for Figure 18-25. Table 18-9.
General Operation of External Master Transfers Table 18-9. Cycles for External Master Burst Line Access to 32-Bit Port (Continued) Cycle Definition C6–C8 No-wait state data transfers 2–4 occur on the rising edges of CLKIN. TA continues to be asserted indicating completion of each transfer. TIP, CSx, and BE/BWE[3:0] are driven. C9 TA negates on the rising edge of CLKIN along with external device’s negation of TIP.
General Operation of External Master Transfers shown in Figure 18-25, the MCF5407 continues to assert BD until the completion of the bus cycle. If BG is negated by the end of the bus cycle, the MCF5407 negates BD. While BG is asserted, BD remains asserted to indicate the MCF5407 is master, and it continuously drives the address bus, attributes, and control signals.
General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 CLKIN A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS AS D[31:0] TA BG BD Implicit Mastership External Master Explicit Mastership MCF5407 Figure 18-28. Two-Wire Implicit and Explicit Bus Mastership In Figure 18-28, the external device is master during C1 and C2. It releases bus control in C3 by asserting BG to the MCF5407. During C4 and C5, the MCF5407 is implicit master because no internal access is pending.
General Operation of External Master Transfers A1 A2 Reset A4 A3 B1 External Master D1 Implicit Master D3 D2 D4 B3 B2 B4 C3 C5 Explicit Master C1 C2 C4 Figure 18-29. MCF5407 Two-Wire Bus Arbitration Protocol State Diagram Table 18-10 describes the two-wire bus arbitration protocol transition conditions. Table 18-10.
General Operation of External Master Transfers 1 Both normal terminations and terminations due to bus errors generate an end of cycle. Bus cycles resulting from a burst-inhibited transfer are considered part of that original transfer. 2 A means asserted. 3 N means negated. 4 EM means external master. 18.9.2 Multiple External Bus Device Arbitration Protocol (Three-Wire Mode) Three-wire mode lets the MCF5407 share the external bus with multiple external devices.
General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 CLKIN A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS AS D[31:0] TA BR BG BD Implicit Mastership External Master Explicit Mastership MCF5407 Figure 18-30. Three-Wire Implicit and Explicit Bus Mastership In Figure 18-30, the external device is bus master during C1 and C2, releasing control in C3, at which time the external arbiter asserts BG to the MCF5407.
General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 CLKIN A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS AS D[31:0] TA BR BG BD External Master MCF5407 Figure 18-31. Three-Wire Bus Arbitration In Figure 18-31, the external device is bus master during C1 and C2. During C2, the MCF5407 requests the external bus because of a pending internal transfer. On C3, the external releases mastership and the external arbiter grants the bus to the MCF5407 by asserting BG.
General Operation of External Master Transfers A1 A2 Reset A4 A3 D1 B1 External Master Implicit Master D3 D2 D4 B3 B2 B4 C3 C5 Explicit Master C1 C2 C4 Figure 18-32. Three-Wire Bus Arbitration Protocol State Diagram Table 18-11 lists conditions that cause state transitions. Table 18-11.
Reset Operation Table 18-11.
Reset Operation 18.10.1 Master Reset To perform a master reset, an external device asserts RSTI. When power is applied to the system, external circuitry should assert RSTI for a minimum of 16 CLKIN cycles after EVcc and IVcc are within tolerance. Figure 18-33 is a functional timing diagram of the master reset operation, showing relationships among E/IVcc, RSTI, mode selects, and bus signals. CLKIN must be stable by the time E/IVcc reach the minimum operating specification. See Section 20.1.
Reset Operation Table 18-12. Data Pin Configuration Pin D7 D[6:5] Function Auto-Acknowledge Configuration (AA_CONFIG) Port Size Configuration (PS_CONFIG[1:0]) D4 Address Configuration (ADDR_CONFIG/D4) D3 Byte Enable Configuration (BE_CONFIG) D[2:0] Divide Control (DIVIDE[2:0]) See Section 17.5.5, “Data/Configuration Pins (D[7:0]).” Motorola recommends that the data pins be driven rather than using a weak pull-up or pull-down resistor. Table 17-1 lists the encoding of these pins sampled at reset.
Reset Operation During the software watchdog reset period, all signals that can be are driven to a high-impedance state; all those that cannot be are negated. When RSTO negates, bus signals remain in a high-impedance state until the MCF5407 is granted the bus and the ColdFire core begins the first bus cycle for reset exception processing.
Chapter 19 IEEE 1149.1 Test Access Port (JTAG) This chapter describes configuration and operation of the MCF5407 JTAG test implementation. It describes the use of JTAG instructions and provides information on how to disable JTAG functionality. 19.1 Overview The MCF5407 dedicated user-accessible test logic is fully compliant with the publication Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1.
JTAG Signal Descriptions that this logic does not affect system or debug operation. Figure 19-1 is a block diagram of the MCF5407 implementation of the 1149.1 IEEE standard. The test logic includes several test data registers, an instruction register, instruction register control decode, and a 16-state dedicated TAP controller. Test Data Registers V+ TDI Boundary Scan Register M U X ID Code Bypass 3-Bit Instruction Decode 3-Bit Instruction Register M U X TDO V+ TMS TCK TAP V+ TRST Figure 19-1.
TAP Controller Table 19-1. JTAG Pin Descriptions Pin Description TCK Test clock. The dedicated JTAG test logic clock is independent of the MCF5407 processor clock. Various JTAG operations occur on the rising or falling edge of TCK. Internal JTAG controller logic is designed such that holding TCK high or low indefinitely does cause the JTAG test logic to lose state information. If TCK is not used, it should be tied to ground. TMS/ BKPT Test mode select (MTMOD0 high)/breakpoint (MTMOD0 low).
JTAG Register Descriptions 1 Test-Logic-Reset TLR 0 Run-Test-Idle 0 <-- Value of TMS at rising edge of TCK 1 1 1 Select-IR-Scan SeIR Select-DR-Scan SeDR RTI 0 0 1 1 Capture-DR CaDR Capture-IR CaIR 0 0 Shift-IR Shift-DR ShDR 0 1 1 Exit1-DR Exit1-IR 1 E1DR 0 Pause-DR PaDR Pause-IR PaIR 0 1 0 1 0 Exit2-DR E2DR Exit2-IR E2IR 1 1 Update-DR UpDR 1 1 E1IR 0 0 0 ShIR 0 Update-IR UpIR 1 0 Figure 19-2. JTAG TAP Controller State Machine 19.
JTAG Register Descriptions 19.4.1 JTAG Instruction Shift Register The MCF5407 IEEE Standard 1149.1 implementation uses a 3-bit instruction-shift register (IR) without parity. This register transfers its value to a parallel hold register and applies one of six instructions on the falling edge of TCK when the TAP state machine is in Update-IR state. To load instructions into the shift portion of the register, place the serial data on TDI before each rising edge of TCK.
JTAG Register Descriptions Table 19-2. JTAG Instructions (Continued) Instruction Class IR Description CLAMP (CMP) Optional 110 Selects the bypass register and asserts functional reset while forcing all output and bidirectional pins configured as outputs to fixed, preloaded values in the boundary-scan update registers. Enhances test efficiency by reducing the overall shift path to one bit (the bypass register) while conducting an EXTEST type of instruction through the boundary-scan register.
JTAG Register Descriptions 19.4.3 JTAG Boundary-Scan Register The MCF5407 model includes an IEEE Standard 1149.1-compliant boundary-scan register connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instructions are selected. This register captures signal data on the input pins, forces fixed values on the output pins, and selects the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state pins.
JTAG Register Descriptions Table 19-4. Boundary-Scan Bit Definitions Bit Cell Type 29 O.Pin 30 O.Pin 31 O.Pin PSTDDATA0 O 151 32 O.Pin PSTCLK O 152 33 I.Pin CLKIN I 153 O.Pin 34 IO.Ctl RSTO enable — 154 35 O.Pin RSTO I/O 155 36 I.Pin RSTO I/O 156 37 O.Pin BCLKO O 157 38 I.Pin EDGESEL I 39 O.Pin TXD0 40 I.Pin RXD0 41 O.Pin RTS0 42 I.Pin CTS0 43 O.Pin TXD1 44 I.Pin 45 O.Pin 46 I.Pin CTS1 I 166 I.Pin PP15 I/O 47 I.Pin HIZ I 167 O.
JTAG Register Descriptions Table 19-4. Boundary-Scan Bit Definitions Bit Cell Type Pin Cell Pin Type Bit Cell Type Pin Cell 65 O.Pin D8 I/O 185 O.Pin PP9 I/O 66 I.Pin D8 I/O 186 IO.Ctl PP8 enable — 67 O.Pin D9 I/O 187 I.Pin PP8 I/O 68 I.Pin D9 I/O 188 O.Pin PP8 I/O 69 O.Pin D10 I/O 189 IO.Ctl TS/R/W/SIZ enable — 70 I.Pin D10 I/O 190 IO.Ctl Address enable — 71 O.Pin D11 I/O 191 O.Pin A23 I/O 72 I.Pin D11 I/O 192 I.Pin A23 I/O 73 O.
Restrictions Table 19-4. Boundary-Scan Bit Definitions Bit Cell Type 101 O.Pin 102 I.Pin 103 104 105 Pin Cell Pin Type Bit Cell Type Pin Cell Pin Type D26 I/O 221 O.Pin A8 I/O D26 I/O 222 I.Pin A8 I/O O.Pin D27 I/O 223 O.Pin A7 I/O I.Pin D27 I/O 224 I.Pin A7 I/O O.Pin D28 I/O 225 O.Pin A6 I/O 106 I.Pin D28 I/O 226 I.Pin A6 I/O 107 O.Pin D29 I/O 227 O.Pin A5 I/O I/O 108 I.Pin D29 I/O 228 I.Pin A5 109 O.Pin D30 I/O 229 O.
Obtaining the IEEE Standard 1149.1 • Nonuse of JTAG test logic by either nontermination (disconnection) or intentionally fixing TAP logic values. The following issues must be addressed if IEEE Standard 1149.1 logic is not to be used when the MCF5407 is assembled onto a board. — IEEE Standard 1149.1 test logic must remain transparent and benign to the system logic during functional operation.
Obtaining the IEEE Standard 1149.1 obtained directly from the IEEE: IEEE Standards Department 445 Hoes Lane P.O. Box 1331 Piscataway, NJ 08855-1331 USA http://stdsbbs.ieee.
Chapter 20 Electrical Specifications This chapter describes the AC and DC electrical specifications and thermal characteristics for the MCF5407. Note that this information was correct at the time this book was published. As process technologies improve, there is a likelihood that this information may change. To confirm that this is the latest information, see Motorola’s ColdFire webpage, http://www.motorola.com/coldfire. 20.
General Parameters Table 20-3 lists DC electrical operating temperatures. This table is based on an operating voltage of EVcc = 3.3 Vdc ± 0.3 Vdc and IVcc of 1.8 ± 0.15 Vdc. Table 20-3. DC Electrical Specifications Characteristic Symbol Min Max Units EVcc 3.0 3.6 V V External (I/O pads) operation voltage range 1 IVcc 1.65 1.95 PVcc 1.65 1.95 V Input high voltage VIH 2.0 3.6 V Internal logic operation voltage range PLL operation voltage range 1 Input low voltage VIL -0.5 0.
General Parameters 20.1.1 Supply Voltage Sequencing and Separation Cautions DC Power Supply Voltage Figure 20-1 shows two situations to avoid in sequencing the IVcc and EVcc supplies. EVcc 3.3V 2 1.8V Supplies Stable IVcc, PVcc 1 0 Time Notes: 1 2 IVcc, PVcc rising before EVcc EVcc rising much faster than IVcc, PVcc Figure 20-1. Supply Voltage Sequencing and Separation Cautions IVcc should not be allowed to rise early (1).
Clock Timing Specifications 3.3 V Regulator Supply EVcc 1.8 V Regulator IVcc, PVcc Figure 20-2. Example Circuit to Control Supply Sequencing 20.2 Clock Timing Specifications Table 20-4 shows the MCF5407 PLL encodings. Note that they differ from the MCF5307 DIVIDE[1:0] encodings. Table 20-4. Divide Ratio Encodings D[2:0]/DIVIDE[2:0] Input Clock (MHz) Multiplier 011 40.0–54.0 3 120.0–162 60.0–81.0 100 25.0–40.5 4 100.0–162 50.0–81.0 101 25.0–32.4 5 125.0–162 67.5–81.0 110 25.0–27.
Clock Timing Specifications PCLK. Although either signal can be used as a clock reference, CLKIN leaves more room to meet the bus specifications than BCLKO, which is generated as a phase-aligned signal to CLKIN. Table 20-5. Clock Timing Specification 54 MHz CLKIN Num Characteristic Units Min Max 18.5 Note 1 nS C1 CLKIN cycle time C2 CLKIN rise time (0.5V to 2.4 V) — 2 nS C3 CLKIN fall time (2.4V to 0.5 V) — 2 nS C4 CLKIN duty cycle (at 1.
Input/Output AC Timing Specifications C5 C6 PSTCLK C6 Figure 20-5. PSTCLK Timing 20.3 Input/Output AC Timing Specifications Table 20-6 lists specifications for parameters shown in Figure 20-6 and Figure 20-7. Note that inputs IRQ[7,5,3,1], BKPT, and AS are synchronized internally; that is, the logic level is validated if the value does not change for two consecutive rising CLKIN edges. Setup and hold times must be met only if recognition on a particular clock edge is required. Table 20-6.
Input/Output AC Timing Specifications Table 20-7. Output AC Timing Specification (Continued) Num 54 MHz CLKIN Characteristic Units Min Max — 0.5(C1) +8.0 9 nS — 0.5(C1) +10.0 10 nS 0.5(C1) + 1.
Input/Output AC Timing Specifications S0 CLKIN S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 B11 B10 A[31:0] TM[2:0] TT[1:0] SIZ[1:0] R/W B11 TS TIP B14 B13 AS, CS, OE BE/BWE[3:0] B12 B2 B10 D[31:0] B1 B5 TA Figure 20-6. AC Timings—Normal Read and Write Bus Cycles Figure 20-7 shows timings for a read cycle with EDGESEL tied to buffered CLKIN.
Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLKIN B6 EDGESEL B15 Row A[31:0] Column TS B16 SRAS B15 SCAS 1 B16 DRAMW B1 D[31:0] B16 B2 RAS B16 CAS ACTV 1 DACR[CASL] NOP READ NOP NOP PALL NOP =2 Figure 20-7. SDRAM Read Cycle with EDGESEL Tied to Buffered CLKIN Figure 20-8 shows an SDRAM write cycle with EDGESEL tied to buffered CLKIN. Chapter 20.
Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 CLKIN B6 EDGESEL B15 Row A[31:0] Column TS B16 SRAS B15 SCAS 1 B16 DRAMW B15 D[31:0] B16 RAS B16 CAS NOP ACTV 1 DACR[CASL] WRITE NOP PALL =2 Figure 20-8. SDRAM Write Cycle with EDGESEL Tied to Buffered CLKIN Figure 20-9 shows an SDRAM read cycle with EDGESEL tied high.
Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLKIN B10 Row A[31:0] Column TS B11 SRAS B10 SCAS 1 B11 DRAMW B1 D[31:0] B11 B2 RAS B11 CAS ACTV 1 DACR[CASL] NOP READ NOP NOP PALL =2 Figure 20-9. SDRAM Read Cycle with EDGESEL Tied High Figure 20-10 shows an SDRAM write cycle with EDGESEL tied high. Chapter 20.
Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 CLKIN B10 Row A[31:0] Column TS B11 SRAS B10 SCAS1 B11 DRAMW B10 D[31:0] B11 RAS B11 CAS ACTV 1 DACR[CASL] NOP WRITE NOP PALL =2 Figure 20-10. SDRAM Write Cycle with EDGESEL Tied High Figure 20-11 shows an SDRAM read cycle with EDGESEL tied low.
Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLKIN B13 Row A[31:0] Column TS B14 SRAS B13 SCAS1 B14 DRAMW B1 D[31:0] B14 B2 RAS B14 CAS ACTV 1 DACR[CASL] NOP READ NOP NOP PALL =2 Figure 20-11. SDRAM Read Cycle with EDGESEL Tied Low Figure 20-12 shows an SDRAM write cycle with EDGESEL tied low. Chapter 20.
Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 CLKIN B13 Row A[31:0] Column TS B14 SRAS B13 SCAS1 B14 DRAMW B13 D[31:0] B14 RAS B14 CAS ACTV 1 DACR[CASL] NOP WRITE NOP PALL =2 Figure 20-12. SDRAM Write Cycle with EDGESEL Tied Low Figure 20-13 shows AC timing showing high impedance. HIZ H1 OUTPUTS Figure 20-13.
Reset Timing Specifications 20.4 Reset Timing Specifications Table 20-8 lists specifications for the reset timing parameters shown in Figure 20-14. Table 20-8. Reset Timing Specification 54 MHz CLKIN Num Characteristic Units Min Max R1 1 Valid to CLKIN (setup) 7.5 — nS R2 CLKIN to invalid (hold) 1.0 — nS R3 RSTI to invalid (hold) 1.0 — nS 1 RSTI and D[7:0] are synchronized internally. Setup and hold times must be met only if recognition on a particular clock is required.
Debug AC Timing Specifications 20.5 Debug AC Timing Specifications Table 20-9 lists specifications for the debug AC timing parameters shown in Figure 20-16. Table 20-9. Debug AC Timing Specification 54 MHz CLKIN Num Characteristic Units Min Max D1 PSTDDATA to PSTCLK setup 4.5 — nS D2 PSTCLK to PSTDDATA hold 4.5 — nS D3 DSI-to-DSCLK setup 1 — PSTCLKs D4 1 DSCLK-to-DSO hold 4 — PSTCLKs D5 DSCLK cycle time 5 — PSTCLKs 1 DSCLK and DSI are synchronized internally.
Timer Module AC Timing Specifications 20.6 Timer Module AC Timing Specifications Table 20-10 lists specifications for timer module AC timing parameters shown in Figure 20-17. Table 20-10. Timer Module AC Timing Specification 54 MHz CLKIN Num Characteristic Units Min Max T1 TIN cycle time 3 — Bus clocks T2 TIN valid to CLKIN (input setup) 7.5 — nS T3 CLKIN to TIN invalid (input hold) 1.0 — nS T4 CLKIN to TOUT valid (output valid) — 10 nS T5 CLKIN to TOUT invalid (output hold) 1.
I2C Input/Output Timing Specifications 20.7 I2C Input/Output Timing Specifications Table 20-11 lists specifications for the I2C input timing parameters shown in Figure 20-18. Table 20-11. I2C Input Timing Specifications between SCL and SDA 54 MHz CLKIN Num Characteristic Units Min Max I1 Start condition hold time 2 — Bus clocks I2 Clock low period 8 — Bus clocks I3 SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — 1 mS I4 Data hold time 0 — nS I5 SCL/SDA fall time (VIH = 2.
UART Module AC Timing Specifications I2 I6 I5 SCL I1 I4 I3 I8 I9 I7 SDA Figure 20-18. I2C Input/Output Timings 20.8 UART Module AC Timing Specifications Table 20-13 lists specifications for UART module AC timing parameters in Figure 20-19. Table 20-13. UART Module AC Timing Specifications 54 MHz CLKIN Num Characteristic Units Min Max U1 RXD valid to CLKIN (input setup) 7.5 — U2 CLKIN to RXD invalid (input hold) 1.0 — nS nS U3 CTS valid to CLKIN (input setup) 7.
UART Module AC Timing Specifications CLKIN U1 RXD U2 U3 CTS U4 U5 TXD U6 U7 RTS U8 Figure 20-19. UART0 and UART1 Module AC Timing—UART Mode Figure 20-19 shows timing for UART1 in 8- and 16-bit CODEC mode.
UART Module AC Timing Specifications U9 U10 CTS/ Serial bit clock U11 TxD U14 U12 U13 RxD TIN1/ Frame sync U15 U16 Figure 20-20. UART1 in 8- and 16-bit CODEC Mode Figure 20-21 shows timing for UART1 in AC ‘97 mode. U9 U10 CTS/ Bit clock U17 RTS/ Frame sync Figure 20-21. UART1 in AC ‘97 Mode Chapter 20.
Parallel Port (General-Purpose I/O) Timing Specifications 20.9 Parallel Port (General-Purpose I/O) Timing Specifications Table 20-14 lists specifications for general-purpose I/O timing parameters in Figure 20-22. Table 20-14. General-Purpose I/O Port AC Timing Specifications 54 MHz CLKIN Num Characteristic Units Min Max P1 PP valid to CLKIN (input setup) 7.5 — nS P2 CLKIN to PP invalid (input hold) 1.
DMA Timing Specifications 20.10 DMA Timing Specifications Table 20-14 lists specifications for DMA timing parameters shown in Figure 20-22. Table 20-15. DMA AC Timing Specifications 54 MHz CLKIN Num Characteristic Units Min Max M1 DREQ valid to CLKIN (input setup) 7.5 — nS M2 CLKIN to DREQ invalid (input hold) 1.0 — nS M3 CLKIN to DACK valid (output valid) — 10 nS M4 CLKIN to DACK invalid (output hold) 1.0 — nS Figure 20-23 shows DMA AC timing.
IEEE 1149.1 (JTAG) AC Timing Specifications 20.11 IEEE 1149.1 (JTAG) AC Timing Specifications Table 20-16 lists specifications for JTAG AC timing parameters shown in Figure 20-24. Table 20-16. IEEE 1149.1 (JTAG) AC Timing Specifications Num Characteristic — TCK frequency of operation Units Min Max 0 10 MHz nS J1 TCK cycle time 100 — J2a TCK clock pulse high width (measured at 1.5 V) 40 — nS J2b TCK clock pulse low width (measured at 1.5 V) 40 — nS J3a TCK fall time (VIH = 2.
IEEE 1149.1 (JTAG) AC Timing Specifications J3a J1 TCK J2b J2a J3b J4 TDI, TMS J5 J6 BOUNDARY SCAN DATA INPUT J7 TRST J8 J9 TDO J10 BOUNDARY SCAN DATA OUTPUT J11 J12 Figure 20-24. IEEE 1149.1 (JTAG) AC Timing Chapter 20.
IEEE 1149.
Appendix A Migrating from the ColdFire MCF5307 to the MCF5407 This appendix highlights the differences between the MCF5307B and MCF5407. Users of the MCF5307 and MCF5307A should use this document in conjunction with the MCF5307 User's Manual Mask Set Addendum. For additional information, see the MCF5407 Integrated ColdFire Microprocessor Product Brief. A.
Instruction Set Additions Table A-1. Differences between MCF5307 and MCF5407 Feature Caches MCF5307 MCF5407 Reference 8-Kbyte unified cache 16-Kbyte instruction cache 8-Kbyte data cache Two cache access control registers (ACR0/ACR1) ACR0/ACR1 configure data space; ACR2/ACR3 configure instruction space 4-Kbyte SRAM Two independently configurable 2-Kbyte SRAMs No cache locking Ability to lock all or half of the caches to prevent instructions or data from being cast out.
Enhanced Memories word-sized operands and position-independent code. Existing MCF5307 code is completely upward compatible with the MCF5407. However, designers may incorporate the instruction set additions and enhancements, especially when upgrading 68K code that references 8- and 16-bit short operands. The following list summarizes new and enhanced instructions of Rev B ISA: • • New instructions: — INTOUCH loads instructions one cache block at a time for use with cache locking. — MOV3Q.
On-Chip DMA Modifications Table A-2.
UART Enhancements Table A-3. TM[2:1] Encoding for MCF5307 Internal DMA as Master (TT = 01) (ConTM[2:1] Transfer Modifier Encoding 10 DMA acknowledge, channel 1 11 Reserved Table A-4. TM0 Encoding for MCF5307 Internal DMA as Master (TT = 01) TM0 Transfer Modifier Encoding 0 Dual address access 1 Single address access Although the MCF5407 provides similar encodings on TM[2:0], dedicated DMA acknowledgement pins (DACK[1:0]) have been added.
Timing Differences The UART module interfaces directly to the CPU as shown in Figure A-2.
Timing Differences CLKIN (to on-chip peripherals) BCLKO PCLK (to core) CLKIN DIVIDE[2:0] Debug Module ÷2 PLL RSTI RSTO Figure A-3. PLL Module PSTCLK (= PCLK/2) Similar to the MCF5307 functionality, the MCF5407 samples clock ratio encodings on the lower data bits of the bus at reset to determine the CLKIN-to-PCLK ratio at which the device runs. These bits are DIVIDE[1:0] on the MCF5307 and are multiplexed with data bits D[1:0].
Reset Initialization Modifications BCLKO runs at the same frequency as CLKIN and is offered as an optional timing reference for backwards compatibility for lower-speed MCF5307 designs. Regardless of the CLKIN frequency driven at power-up, CLKIN and BCLKO have the same ratio value to PCLK.
Reset Initialization Modifications multiplexed with D[7:3]. See for D[2:0]/DIVIDE[2:0] encodings sampled at reset. Note that Table A-7 and Table A-8 configure the global, or boot, CS0 that is used to access boot ROM out of reset. CS0 is the only chip select active out of reset until other chip selects become valid. Both the wait states and port size of boot memory accessed by boot CS0 are programmed through these bits. Table A-7.
Revision C Debug 0xCF4x_C012 identify the MCF5407, where x identifies the core revision number (0x1 for the initial device). A.8 Revision C Debug A number of enhancements to the original ColdFire debug functions were requested by customers and third-party tool developers. As a result, an expanded set of debug functions was implemented in the Version 4 ColdFire and named Revision C, or simply Debug C.
Revision C Debug frame, shown in Figure A-4. 31 A7→ + 0x04 28 Format 27 26 FS[3–2] 25 18 Vector[7–0] 17 16 15 FS[1–0] 0 Status Register Program counter[31:0] Figure A-4. Exception Stack Frame Form As part of the Debug C enhancement, the operation of the debug interrupt is modified as follows: • • • 1. 2. 3. 4. The occurrence of the breakpoint trigger, configured to generate a debug interrupt, is treated exactly as before.
Revision C Debug A.8.2 On-Chip Breakpoint Registers The Debug B core debug module included three basic types of on-chip breakpoint registers: • • • A 32-bit PC breakpoint register and a 32-bit PC breakpoint mask Two 32-bit address registers, which can be used to specify a single address or a range of addresses A 32-bit data breakpoint register and a 32-bit data breakpoint mask The mask registers can be used to “don’t care” the equivalent bits in the breakpoint registers.
Revision C Debug Table A-11 describes the DRc encoding for the debug registers. Table A-11.
Revision C Debug Command complete status (0x0FFFF) is returned when register write is complete. A.8.3 Debug Programming Model In addition to existing BDM commands that provide access to the processor’s registers and the memory subsystem, the debug module contains a number of registers to support the required functionality. These registers are treated as 32-bit quantities, regardless of the number of bits in the implementation.
Revision C Debug The results of all PC breakpoint registers, PBR/PBMR, PBR1, PBR2, and PBR3, are logically summed to form a single PC breakpoint trigger signal. • • PBRn[31:1] = program counter breakpoint address PBRn[0] = valid bit A.8.3.4 Data Breakpoint Register 1 (DBR1, DBMR1) The data breakpoint register 1 (DBR1) defines a specific data pattern that can be used as part of a trigger.
Revision C Debug Table A-12. Debug C Exception Vector Assignments Vector Vector Offset Stacked Program Counter Assignment 12 0x030 Next Non-PC-breakpoint debug interrupt 13 0x034 Next PC-breakpoint debug Interrupt A.8.5 Processor Status and Debug Data Output Signals The Debug B architecture defines processor status, PST[3:0] and debug data DDATA[3:0] signals, which provide information to support real-time trace. In the Debug B design, these signals are output at the processor frequency.
Voltage Input Changes Table A-13.
Pin-Assignment Compatibility circuit similar to the one shown in Figure A-7. The circuit should be as close as possible to the PLL power pin to ensure maximum noise filtering. This filter design can be used for both the MCF5307 and MCF5407. . Vdd 10 Ω PLL power pin 10 µF 0.1 µF Figure A-7. PLL Power Supply Filter Circuit A.
Appendix B List of Memory Maps Table B-1. SIM Registers MBAR Offset 0x000 0x004 [31:24] [23:16] [15:8] [7:0] Reset status register (RSR) [p. 6-5] System protection control register (SYPCR) [p. 6-8] Software watchdog interrupt vector register (SWIVR) [p. 6-9] Software watchdog service register (SWSR) [p. 6-9] Interrupt port assignment register (IRQPAR) [p. 9-7] Reserved Pin assignment register (PAR) [p. 6-10] 0x008 PLL control (PLLCR) [p.
Table B-3. Chip-Select Registers MBAR Offset 0x080 0x084 [31:24] [23:16] [15:8] [7:0] Reserved1 Chip-select address register—bank 0 (CSAR0) [p. 10-6] Chip-select mask register—bank 0 (CSMR0) [p. 10-7] 0x088 Reserved1 Chip-select control register—bank 0 (CSCR0) [p. 10-8] 0x08C Chip-select address register—bank 1 (CSAR1) [p. 10-6] Reserved1 0x090 Chip-select mask register—bank 1 (CSMR1) [p. 10-7] 0x094 Reserved1 Chip-select control register—bank 1 (CSCR1) [p.
Table B-3. Chip-Select Registers (Continued) MBAR Offset [31:24] [23:16] [15:8] [7:0] MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x080 0x084 Chip-select mask register—bank 0 (CSMR0) [p. 10-7] 0x088 Reserved1 Chip-select control register—bank 0 (CSCR0) [p. 10-8] 0x08C Chip-select address register—bank 1 (CSAR1) [p. 10-6] Reserved1 0x090 Chip-select mask register—bank 1 (CSMR1) [p. 10-7] 0x094 Reserved1 Chip-select control register—bank 1 (CSCR1) [p.
Table B-5. General-Purpose Timer Registers MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x140 Timer 0 mode register (TMR0) [p. 13-3] 0x144 Timer 0 reference register (TRR0) [p. 13-4] Reserved 0x148 Timer 0 capture register (TCR0) [p. 13-4] Reserved 0x14C 0x150 Reserved Timer 0 counter (TCN0) [p. 13-5] Reserved Reserved Timer 0 event register (TER0) [p. 13-5] Reserved 0x180 Timer 1 mode register (TMR1) [p. 13-3] 0x184 Timer 1 reference register (TRR1) [p.
Table B-6. UART0 Control Registers (Continued) MBAR Offset [31:24] [23:16] (Read) UART input port change registers—(UIPCRn) [p. 14-17] — (Write) UART auxiliary control registers1—(UACRn) [p. 14-17] — (Read) UART interrupt status registers—(UISRn) [p. 14-18] — (Write) UART interrupt mask registers—(UIMRn) [p. 14-18] — 0x1D8 UART divider upper registers—(UDUn) [p. 14-19] — 0x1DC UART divider lower registers—(UDLn) [p.
3 Address-triggered commands Table B-7. UART1 Control Registers MBAR Offset [31:24] [23:16] [15:8] [7:0] UART1 Control Registers 0x200 UART mode registers1—(UMR1n)[p. 14-5], (UMR2n) [p. 14-7 Rx FIFO threshold register—(RXLVL) [p. 14-8] Modem control register—(MODCTL) [p. 14-9] Tx FIFO threshold register—(TXLVL) [p. 14-10] 0x204 (Read) UART status registers—(USRn) [p. 14-10] — (Read) Rx samples available register—(RSMP) [p. 14-12] (Read) Tx space available register—(TSPC) [p.
Table B-7. UART1 Control Registers (Continued) MBAR Offset [31:24] [23:16] 0x230 UART interrupt vector register—(UIVRn) [p. 14-20] — 0x234 (Read) UART input port registers—(UIPn) [p. 14-20] — 2 (Write) Do not access 0x238 2 [15:8] [7:0] — (Read) Do not access — (Write) UART output port bit set command registers—(UOP1n3) [p. 14-21] — (Read) Do not access 2 — (Write) UART output port bit reset command registers—(UOP0n3) [p. 14-21] — 0x200 UART mode registers4—(UMR1n) [p.
Table B-9. I2C Interface Memory Map MBAR Offset [31:24] [23:16] [15:8] 0x280 I2C address register (IADR) [p. 8-6] Reserved 0x284 I2C frequency divider register (IFDR) [p. 8-6] Reserved 0x288 I2C control register (I2CR) [p. 8-7] Reserved 0x28C I2C status register (I2SR) [p. 8-8] Reserved 0x290 I2C data I/O register (I2DR) [p. 8-9] Reserved [7:0] Table B-10. DMA Controller Registers MBAR Offset [31:24] [23:16] [15:8] 0x300 Source address register 0 (SAR0) [p.
Table B-10. DMA Controller Registers (Continued) MBAR Offset 0x394 [31:24] DMA interrupt vector register 2 (DIVR2) [p. 12-11] [23:16] [15:8] Reserved 0x3C0 Source address register 3 (SAR3) [p. 12-7] 0x3C4 Destination address register 3 (DAR3) [p. 12-7] 0x3C8 [7:0] DMA control register 3 (DCR3) [p. 12-8] 0x3CC Reserved Byte count register 3 (BCR3) [p. 12-7] 0x3D0 DMA status register 3 (DSR3) [p. 12-10] Reserved 0x3D4 DMA interrupt vector register 3 (DIVR3) [p. 12-11] Reserved Appendix B.
B-10 MCF5407 User’s Manual
Glossary of Terms and Abbreviations The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. A Architecture. A detailed specification of requirements for a processor or computer system. It does not specify details of how the processor or computer system must be implemented; instead it provides a template for a family of compatible implementations. Autovector.
system. Caches are coherent if a processor performing a read from its cache is supplied with data corresponding to the most recent value written to memory or to another processor’s cache. Cache flush. An operation that removes from a cache any data from a specified address range. This operation ensures that any modified data within the specified address range is written back to main memory. Cache line. The smallest unit of consecutive data or instructions that is stored in a cache.
H I Illegal instructions. A class of instructions that are not implemented for a particular processor. These include instructions not defined by the ColdFire architecture. Implementation. A particular processor that conforms to the ColdFire architecture, but may differ from other architecture-compliant implementations for example in design, feature set, and implementation of optional features. The ColdFire architecture has many different implementations. Imprecise mode.
Most-significant bit (msb). The highest-order bit in an address, registers, data element, or instruction encoding. Most-significant byte (MSB). The highest-order byte in an address, registers, data element, or instruction encoding. N O P Nop. No-operation. A single-cycle operation that does not affect registers or generate bus activity. Overflow. An condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register(s).
Superscalar machine. A machine that can issue multiple instructions concurrently from a conventional linear instruction stream. Supervisor mode. The privileged operation state of a processor. In supervisor mode, software, typically the operating system, can access all control registers and can access the supervisor memory space, among other privileged operations. System memory. The physical memory available to a processor. T Tenure. A tenure consists of three phases: arbitration, transfer, termination.
Glossary-6 MCF5407 User’s Manual
INDEX A C Addressing mode summary, 2-15 Arbitration between masters, 6-14 bus control, 6-11 for internal transfers, 6-12 Architecture Harvard memory, 2-6 instruction set additions, 2-18 enhancements, 2-36 Cache configuration register, 2-12 registers, access control, 2-12 Chip-select module 8-, 16-, and 32-bit port sizing, 10-4 enable signals, 17-15 operation, 10-2 general, 10-3 global, 10-4 overview, 10-1 registers, 10-5, 10-6, B-2 code example, 10-9 control, 10-8 mask, 10-7 signals, 10-1 Clock PLL contr
INDEX address and control, 11-5 mask, 11-7 signals, 17-16 synchronous operation, 11-16 address and control registers, 11-20 address multiplexing, 11-23 auto-refresh, 11-31 burst page mode, 11-27 continuous page mode, 11-29 controller signals, synchronous mode, 11-17 edge select, 11-18 general guidelines, 11-23 initialization, 11-32 interfacing, 11-27 mask registers, 11-22 mode register settings, 11-33 register set, 11-19 self-refresh, 11-32 E Electrical specifications cautions, 20-3 clock timing, 20-4 debu
INDEX Pipelines, 2-2 instruction fetch, 2-4 operand execution, 2-4 PLL, 7-2 clock control for STOP, 6-10 clock frequency relationships, 7-4 clock-multiplied, 2-2 control register, 7-3 modes normal, 7-2 reduced power, 7-3 operation, 7-2 overview, 7-1 port list, 7-4 power supply filter circuit, 7-6 reset/initialization, 7-2 timing relationships, 7-4 Power supply filter circuit, 7-6 Program counter, 2-9 Programming models MAC, 2-10 overview, 2-7 registers, 1-15 SIM, 6-3 summary, B-1 supervisor, 2-10 user, 2-8
INDEX asynchronous address and control, 11-5 DACR, 11-5 DCR, 11-4 DMR, 11-7 mode signals, 11-4 general operation, 11-3 synchronous DACR, 11-20 DCR, 11-19 DMR, 11-22 mode settings, 11-33 2 IC address, 8-6 control, 8-7 data I/O, 8-9 frequency divider, 8-6 status, 8-8 I2CR, 8-7 I2DR, 8-9 I2SR, 8-8 IADR, 8-6 IFDR, 8-6 integer data formats in, 2-13 interrupt controller autovector, 9-5 pending and mask, 9-6 port assignment, 9-7 IPR and IMR, 9-6 IRQPAR, 9-7 JTAG boundary scan, 19-7 bypass, 19-10 descriptions, 19-4
INDEX interrupt request, 17-12 JTAG, 19-2 parallel I/O port, 17-19 read/write, 17-8 reset in, out, 17-13 serial module clear to Send, 17-19 general, 17-18 receiver serial data input, 17-19 request to send, 17-19 transmitter serial data output, 17-18 size, 17-8 timer module, 17-19 transfer acknowledge, 17-9 in progress, 17-10 modifier, 17-10 start, 17-9 Signals overview, 17-1 SIM features, 6-1 programming model, 6-3 register memory map, 6-3 Software watchdog interrupt vector register, 6-9 service register, 6
INDEX Transfers internally generated, 6-12 U UART Modules register description and programming register description UART module programming model (table 14-1), B-4 UART modules bus operation, 14-37 interrupt acknowledge cycles, 14-37 read cycles, 14-37 write cycles, 14-37 clock source baud rates, 14-24 controm registers, B-6 external clock, 14-25 FIFO stack in UART0, 14-32 initialization sequence, 14-38 looping modes, 14-34 automatic echo, 14-34 local loop-back, 14-34 remote loop-back mode, 14-35 mode regi
Overview Part I: MCF5407 Processor Core 1 Part I ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 Part II: System Integration Module (SIM) Part II SIM Overview 6 Phase-Locked Loop (PLL) 7 I2C Module 8 Interrupt Controller 9 Chip-Select Module 10 Synchronous/Asynchronous DRAM Controller Module 11 Part III: Peripheral Module Part III DMA Controller Module 12 Timer Module 13 UART Modules 14 Parallel Port (General-Purpose I/O) 15 Part IV
1 Part I Overview Part I: MCF5407 Processor Core 2 ColdFire Core 3 Hardware Multiply/Accumulate (MAC) Unit 4 Local Memory 5 Debug Support Part II Part II: System Integration Module (SIM) 6 SIM Overview 7 Phase-Locked Loop (PLL) 8 I2C Module 9 Interrupt Controller 10 Chip-Select Module 11 Synchronous/Asynchronous DRAM Controller Module Part III Part III: Peripheral Module 12 DMA Controller Module 13 Timer Module 14 UART Modules 15 Parallel Port (General-Purpose I/O) Part IV
