Datasheet

x MCF5407 User’s Manual
CONTENTS
Paragraph
Number
Title
Page
Number
6.2.2 Module Base Address Register (MBAR) ....................................................... 6-4
6.2.3 Reset Status Register (RSR) ........................................................................... 6-5
6.2.4 Software Watchdog Timer.............................................................................. 6-6
6.2.5 System Protection Control Register (SYPCR) ............................................... 6-8
6.2.6 Software Watchdog Interrupt Vector Register (SWIVR)............................... 6-9
6.2.7 Software Watchdog Service Register (SWSR)............................................... 6-9
6.2.8 PLL Clock Control for CPU STOP Instruction ............................................ 6-10
6.2.9 Pin Assignment Register (PAR) ................................................................... 6-10
6.2.10 Bus Arbitration Control ................................................................................ 6-11
6.2.10.1 Default Bus Master Park Register (MPARK) .......................................... 6-11
6.2.10.1.1 Arbitration for Internally Generated Transfers (MPARK[PARK])...... 6-12
6.2.10.1.2 Arbitration between Internal and External Masters
for Accessing Internal Resources ......................................................... 6-14
Chapter 7
Phase-Locked Loop (PLL)
7.1 Overview............................................................................................................. 7-1
7.1.1 PLL:PCLK Ratios........................................................................................... 7-2
7.2 PLL Operation .................................................................................................... 7-2
7.2.1 Reset/Initialization .......................................................................................... 7-2
7.2.2 Normal Mode.................................................................................................. 7-2
7.2.3 Reduced-Power Mode..................................................................................... 7-3
7.2.4 PLL Control Register (PLLCR)...................................................................... 7-3
7.3 PLL Port List....................................................................................................... 7-4
7.4 Timing Relationships.......................................................................................... 7-4
7.4.1 PCLK, PSTCLK, and BCLKO ....................................................................... 7-4
7.4.2 RSTI
Timing ................................................................................................... 7-5
7.5 PLL Power Supply Filter Circuit ........................................................................ 7-6
Chapter 8
I
2
C Module
8.1 Overview............................................................................................................. 8-1
8.2 Interface Features................................................................................................ 8-1
8.3 I
2
C System Configuration................................................................................... 8-3
8.4 I
2
C Protocol ........................................................................................................ 8-3
8.4.1 Arbitration Procedure ..................................................................................... 8-4
8.4.2 Clock Synchronization.................................................................................... 8-5
8.4.3 Handshaking ................................................................................................... 8-5
8.4.4 Clock Stretching ............................................................................................. 8-5
8.5 Programming Model ........................................................................................... 8-6