Datasheet

Chapter 2. ColdFire Core 2-39
ColdFire Instruction Set Architecture Enhancements
BSR Branch to Subroutine BSR
Operation: SP – 4 → SP; PC → (SP); PC + d
n
→ PC
Assembler Syntax: BSR <label>
Attributes: Size = byte, word, long
Description: Pushes the word address of the instruction immediately following the BSR
instruction onto the system stack. The PC contains the address of the instruction word, plus
two. Program execution then continues at location (PC) + displacement. The displacement
is a two’s complement integer that represents the relative distance in bytes from the current
PC to the destination PC. If the 8-bit displacement field in the instruction word is 0, a 16-bit
displacement (the word immediately following the instruction) is used. If the 8-bit
displacement field in the instruction word is all ones (0xFF), the 32-bit displacement
(longword immediately following the instruction) is used.
Condition Codes: Not affected
Instruction Fields:
• 8-bit displacement field—Two’s complement integer specifying the number of bytes
between the branch instruction and the next instruction to be executed.
• 16-bit displacement field—Used for displacement when the 8-bit displacement
contains 0x00.
• 32-bit displacement field—Used for displacement when the 8-bit displacement
contains 0xFF.
NOTE:
A branch to the next immediate instruction automatically uses
the 16-bit displacement format because the 8-bit displacement
field contains 0x00 (zero offset).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction
Format:
01100001 8-bit displacement
16-bit displacement if 8-bit displacement = 0x00
32-bit displacement if 8-bit displacement = 0xFF
BSR V2, V3 Core V4 Core
Opcode present Yes Yes
Operand sizes supported .b, .w .b, .w, .l