Datasheet
CONTENTS
Paragraph
Number
Title
Page
Number
Contents
xi
8.5.1 I
2
C Address Register (IADR)......................................................................... 8-6
8.5.2 I
2
C Frequency Divider Register (IFDR)......................................................... 8-6
8.5.3 I
2
C Control Register (I2CR)........................................................................... 8-7
8.5.4 I
2
C Status Register (I2SR).............................................................................. 8-8
8.5.5 I
2
C Data I/O Register (I2DR) ......................................................................... 8-9
8.6 I
2
C Programming Examples ............................................................................. 8-10
8.6.1 Initialization Sequence.................................................................................. 8-10
8.6.2 Generation of START................................................................................... 8-10
8.6.3 Post-Transfer Software Response................................................................. 8-11
8.6.4 Generation of STOP...................................................................................... 8-12
8.6.5 Generation of Repeated START................................................................... 8-12
8.6.6 Slave Mode ................................................................................................... 8-13
8.6.7 Arbitration Lost............................................................................................. 8-13
Chapter 9
Interrupt Controller
9.1 Overview............................................................................................................. 9-1
9.2 Interrupt Controller Registers ............................................................................. 9-2
9.2.1 Interrupt Control Registers (ICR0–ICR9) ...................................................... 9-3
9.2.2 Autovector Register (AVR) ............................................................................ 9-5
9.2.3 Interrupt Pending and Mask Registers (IPR and IMR)................................... 9-6
9.2.4 Interrupt Port Assignment Register (IRQPAR) .............................................. 9-7
Chapter 10
Chip-Select Module
10.1 Overview........................................................................................................... 10-1
10.2 Chip-Select Module Signals ............................................................................. 10-1
10.3 Chip-Select Operation....................................................................................... 10-2
10.3.1 General Chip-Select Operation..................................................................... 10-3
10.3.1.1 8-, 16-, and 32-Bit Port Sizing.................................................................. 10-4
10.3.1.2 Global Chip-Select Operation................................................................... 10-4
10.4 Chip-Select Registers........................................................................................ 10-5
10.4.1 Chip-Select Module Registers ...................................................................... 10-6
10.4.1.1 Chip-Select Address Registers (CSAR0–CSAR7)................................... 10-6
10.4.1.2 Chip-Select Mask Registers (CSMR0–CSMR7)...................................... 10-7
10.4.1.3 Chip-Select Control Registers (CSCR0–CSCR7) .................................... 10-8
10.4.1.4 Code Example........................................................................................... 10-9
Chapter 11
Synchronous/Asynchronous DRAM Controller Module