Datasheet

Chapter 2. ColdFire Core 2-51
ColdFire Instruction Set Architecture Enhancements
TAS Test and Set an Operand TAS
Operation: Destination Tested → CCR; 1 → bit 7 of Destination
Assembler Syntax: TAS <ea>x
Attributes: Size = byte
Description: Tests and sets the byte operand addressed by the effective address field. The
instruction tests the current value of the operand and sets the N and Z condition code bits
appropriately. TAS also sets the high-order bit of the operand. The operand uses a
read-modify-write memory cycle that completes the operation without interruption. This
instruction supports use of a flag or semaphore to coordinate several processors.
Condition Codes:
Instruction Fields:
• Effective address field—specifies the destination location; the possible data alterable
addressing modes are listed in the table below.
X N Z V C X Not affected
N Set if the msb of the operand is currently set; cleared otherwise
Z Set if the operand was zero; cleared otherwise
V Always cleared
C Always cleared
— ∗∗00
1514131211109876543210
Instruction
Format:
0100101011 EFFECTIVE ADDRESS
MODE REGISTER
Addressing Mode Mode Register Addressing Mode Mode Register
Dx — — (d
8
,Ax,Xi) 110 reg. number:Ax
Ax — — (xxx).W 111 000
(Ax) 010 reg. number:Ax (xxx).L 111 001
(Ax) + 011 reg. number:Ax #<data> — —
– (Ax) 100 reg. number:Ax (d
16
,PC) — —
(d
16
,Ax) 101 reg. number:Ax (d
8
,PC,Xi) — —
TAS V2, V3 Core V4 Core
Opcode present No Yes
Operand sizes supported — .b