Datasheet

4-2 MCF5407 User’s Manual
SRAM Operation
0-modulo-2K location in the 4-Gbyte address space and configured to respond to either
instruction or data accesses. Time-critical functions can be mapped into instruction
memory and the system stack. Other heavily-referenced data can be mapped into data
memory.
The following summarizes features of the MCF5407 SRAM implementation:
• Two 2-Kbyte SRAMs, organized as 512 x 32 bits
• Single-cycle throughput. When the pipeline is full, one access can occur per clock
cycle.
• Physical location on the processor’s high-speed local bus with a user-programmed
connection to the internal instruction or data bus
• Memory location programmable on any 0-modulo-2K address boundary
• Byte, word, and longword address capabilities
• The RAM base address registers (RAMBAR0 and RAMBAR1) define the logical
base address, attributes, and access types for the two SRAM modules.
4.3 SRAM Operation
Each SRAM module provides a general-purpose memory block that the ColdFire processor
can access with single-cycle throughput. The location of the memory block can be specified
to any word-aligned address in the 4-Gbyte address space by RAMBARn[BA], described
in Section 4.4.1, “SRAM Base Address Registers (RAMBAR0/RAMBAR1).” The memory
is ideal for storing critical code or data structures or for use as the system stack. Because
the SRAM module connects physically to the processor’s high-speed local bus, it can
service processor-initiated accesses or memory-referencing debug module commands.
The Version 4 ColdFire processor core implements a Harvard memory architecture. Each
SRAM module may be logically connected to either the processor’s internal instruction or
data bus. This logical connection is controlled by a configuration bit in the RAM base
address registers (RAMBAR0 and RAMBAR1).
If an instruction fetch is mapped into the region defined by the SRAM, the SRAM sources
the data to the processor and any cache data is discarded. Likewise, if a data access is
mapped into the region defined by the SRAM, the SRAM services the access and the cache
is not affected. Accesses from SRAM modules are never cached, and debug-initiated
references are treated as data accesses.
Note also that the SRAMs cannot be accessed by the on-chip DMAs. The on-chip system
configuration allows concurrent core and DMA execution, where the core can reference
code or data from the internal SRAMs or caches while performing a DMA transfer.