Datasheet

4-8 MCF5407 User’s Manual
Cache Organization
4.8 Cache Organization
A four-way set associative cache is organized as four ways (levels). There are 128 sets in
the 8-Kbyte data cache with each line containing 16 bytes (4 longwords). The 16-Kbyte
instruction cache has 256 sets. Entire cache lines are loaded from memory by burst-mode
accesses that cache 4 longwords of data or instructions. All 4 longwords must be loaded for
the cache line to be valid.
Figure 4-3 shows data cache organization as well as terminology used.
Figure 4-3. Data Cache Organization and Line Format
A set is a group of four lines (one from each level, or way), corresponding to the same index
into the cache array.
4.8.1 Cache Line States: Invalid, Valid-Unmodified, and
Valid-Modified
As shown in Table 4-3, a data cache line can be invalid, valid-unmodified (often called
exclusive), or valid-modified. An instruction cache line can be valid or invalid.
A valid line can be explicitly invalidated by executing a CPUSHL instruction.
Table 4-3. Valid and Modified Bit Settings
V M Description
0 x Invalid. Invalid lines are ignored during lookups.
1 0 Valid, unmodified. Cache line has valid data that matches system memory.
1 1 Valid, modified. Cache line contains most recent data, data at system memory location is stale.
Way 0 Way 1 Way 2 Way 3
Line
Set 0
Set 1
Set 126
Set 127
•
•
•
•
•
•
•
•
•
•
•
•
TAG V M Longword 0 Longword 1 Longword 2 Longword 3
Where:
TAG—21-bit address tag
V—Valid bit for line
M—Modified bit for line (data cache only)
Cache Line Format