Datasheet
xiv
MCF5407 User’s Manual
CONTENTS
Paragraph
Number
Title
Page
Number
13.3.5 Timer Event Registers (TER0/TER1)........................................................... 13-5
13.4 Code Example................................................................................................... 13-6
13.5 Calculating Time-Out Values ........................................................................... 13-7
Chapter 14
UART Modules
14.1 Overview........................................................................................................... 14-1
14.2 Serial Module Overview ................................................................................... 14-2
14.3 Register Descriptions ........................................................................................ 14-3
14.3.1 UART Mode Registers 1 (UMR1n).............................................................. 14-5
14.3.2 UART Mode Register 2 (UMR2n) ............................................................... 14-7
14.3.3 Rx FIFO Threshold Register (RXLVL)........................................................ 14-8
14.3.4 Modem Control Register (MODCTL).......................................................... 14-9
14.3.5 Tx FIFO Threshold Register (TXLVL) ...................................................... 14-10
14.3.6 UART Status Registers (USRn) ................................................................. 14-10
14.3.7 UART Clock-Select Registers (UCSRn).................................................... 14-12
14.3.8 Receive Samples Available Register (RSMP)............................................ 14-12
14.3.9 Transmit Space Available Register (TSPC) ............................................... 14-13
14.3.10 UART Command Registers (UCRn) .......................................................... 14-13
14.3.11 UART Receiver Buffers (URBn) ............................................................... 14-15
14.3.12 UART Transmitter Buffers (UTBn) ........................................................... 14-16
14.3.13 UART Input Port Change Registers (UIPCRn).......................................... 14-17
14.3.14 UART Auxiliary Control Register (UACRn)............................................. 14-17
14.3.15 UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 14-18
14.3.16 UART Divider Upper/Lower Registers (UDUn/UDLn) ............................ 14-19
14.3.17 UART Interrupt Vector Register (UIVRn)................................................. 14-20
14.3.18 UART Input Port Register (UIPn) .............................................................. 14-20
14.3.19 UART Output Port Data Registers (UOP1n/UOP0n)................................. 14-21
14.4 UART Module Signal Definitions .................................................................. 14-21
14.5 Operation......................................................................................................... 14-23
14.5.1 Transmitter/Receiver Clock Source............................................................ 14-23
14.5.1.1 Programmable Divider............................................................................ 14-24
14.5.1.2 Calculating Baud Rates........................................................................... 14-24
14.5.1.2.1 CLKIN Baud Rates............................................................................. 14-24
14.5.1.2.2 External Clock .................................................................................... 14-25
14.5.2 Transmitter and Receiver Operating Modes............................................... 14-25
14.5.2.1 Transmitting in UART Mode ................................................................. 14-26
14.5.2.2 Transmitter in Modem Mode (UART1) ................................................. 14-27
14.5.2.2.1 AC ‘97 Low-Power Mode .................................................................. 14-29
14.5.2.3 Receiver .................................................................................................. 14-29
14.5.2.4 UART1 in UART Mode ......................................................................... 14-31