Datasheet

Chapter 4. Local Memory 4-19
Cache Operation
another cache fill is required (for example, cache miss to process) during the continued
instruction execution by the processor pipeline, the pipeline stalls until the push and store
buffers are empty, then generate the required external bus transaction.
Supervisor instructions, the NOP instruction, and exception processing synchronize the
processor core and guarantee the push and store buffers are empty before proceeding. Note
that the NOP instruction should be used only to synchronize the pipeline. The preferred
no-operation function is the TPF instruction.
4.9.6 Cache Locking
Ways 0 and 1 of the data cache can be locked by setting CACR[DHLCK]; likewise, ways
0 and 1 of the instruction cache can be locked by setting CACR[IHLCK]. If a cache is
locked, cache lines in ways 0 and 1 are not subject to being deallocated by normal cache
operations.
As Figure 4-7 (B and C) shows, the algorithm for updating the cache and for identifying
cache lines to be deallocated is otherwise unchanged. If ways 2 and 3 are entirely invalid,
cacheable accesses are first allocated in way 2. Way 3 is not used until the location in way 2
is occupied.
Ways 0 and 1 are still updated on write hits (D in Figure 4-7) and may be pushed or cleared
only explicitly by using specific cache push/invalidate instructions. However, new cache
lines cannot be allocated in ways 0 and 1.