Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller FQFP 208 (28x28) 32-Bit 162 MHz I/O number 16

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Chapter 4. Local Memory 4-21

Cache Registers

4.10 Cache Registers

This section describes the MCF5407 implementation of the Version 4 cache registers.

4.10.1 Cache Control Register (CACR)

The CACR in Figure 4-8 contains bits for conﬁguring the cache. It can be written by the

MOVEC register instruction and can be read or written from the debug facility. A hardware

reset clears CACR, which disables the cache; however, reset does not affect the tags, state

information, or data in the cache.

Table 4-4 describes CACR ﬁelds.

31 30 29 28 27 26 25 24 23 20 19 18 17 16

Field DEC DW DESB DDPI DHLCK DDCM DCINVA —

BEC BCINVA

—

Reset 0000_0000_0000_0000

R/W Write (R/W by debug module)

15 14 13 12 11 10 9 8 7 0

Field IEC — DNFB IDPI IHLCK IDCM — ICINVA —

Reset 0000_0000_0000_0000

R/W Write (R/W by debug module)

Rc 0x002

Figure 4-8. Cache Control Register (CACR)

Table 4-4. CACR Field Descriptions

Bits Name Description

31 DEC Enable data cache.

0 Cache disabled. The data cache is not operational, but data and tags are preserved.

1 Cache enabled.

30 DW Data default write-protect. For normal operations that do not hit in the RAMBARs or ACRs, this

ﬁeld deﬁnes write-protection. See Section 4.9.1, “Caching Modes.”

0 Not write protected.

1 Write protected. Write operations cause an access error exception.

29 DESB Enable data store buffer. Affects the precision of transfers. CACR[DESB] has precedence over

CACR[9–8] and ACRn[9–8]; therefore, the store buffer must be disabled to use imprecise mode.

0 Imprecise-mode, write-through or cache-inhibited writes bypass the store buffer and generate

bus cycles directly. Section 4.9.5.2.1, “Push and Store Buffers,” describes the associated

performance penalty.

1 The four-entry FIFO store buffer is enabled; to maximize performance, this buffer defers

pending imprecise-mode, write-through or cache-inhibited writes.

Precise-mode, cache-inhibited accesses always bypass the store buffer. Precise and imprecise

modes are described in Section 4.9.2, “Cache-Inhibited Accesses.”

28 DDPI Disable CPUSHL invalidation.

0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modiﬁed and

then invalidated.

1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modiﬁed,

then left valid.