Datasheet

Chapter 4. Local Memory 4-27
Cache Operation Summary
;instruction cache
lea 16(a0),a0 ;increment address to next line
subq.l #1,d0 ;decrement loop counter
bne.b instCacheLoop ;if done, then exit, else continue
; A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache.
; lock it!
move.l #0xa2088800,d0 ;set the instruction cache lock bit
movec d0,cacr ;in the CACR
rts
4.12 Cache Operation Summary
This section gives operational details for the cache and presents instruction and data
cache-line state diagrams.
4.12.1 Instruction Cache State Transitions
Because the instruction cache does not support writes, it supports fewer operations than the
data cache. As Figure 4-12 shows, an instruction cache line can be in one of two states, valid
or invalid. Modified state is not supported. Transitions are labeled with a capital letter
indicating the previous state and with a number indicating the specific case listed in
Table 4-6. These numbers correspond to the equivalent operations on data caches,
described in Section 4.12.2, “Data Cache State Transitions.”
Figure 4-12. Instruction Cache Line State Diagram
Table 4-6 describes the instruction cache state transitions shown in Figure 4-12.
Table 4-6. Instruction Cache Line State Transitions
Access
Current State
Invalid (V = 0) Valid (V = 1)
Read miss II1 Read line from memory and update cache;
supply data to processor;
go to valid state.
IV1 Read new line from memory and update cache;
supply data to processor; stay in valid state.
Read hit II2 Not possible IV2 Supply data to processor;
stay in valid state.
Write miss II3 Not possible IV3 Not possible
Write hit II4 Not possible IV4 Not possible
Valid
V = 1
II5—ICINVA
II6—CPUSHL & IDPI
II7—CPUSHL & IDPI
IV1—CPU read miss
IV2—CPU read hit
IV7—CPUSHL & IDPI
IV5—ICINVA
IV6—CPUSHL & IDPI
Invalid
V = 0
II1—CPU read miss