Datasheet

4-30 MCF5407 User’s Manual
Cache Operation Summary
The following tables present the same information as Table 4-7, organized by the current
state of the cache line. In Table 4-8 the current state is invalid.
In Table 4-9 the current state is valid.
Write hit
(write-
through)
WI4 Not possible. WV4 Write data to memory and
to cache;
stay in valid state.
WD4 Write data to memory and
to cache;
go to valid state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[DCINVA,ICINVA]
before switching modes.
Cache
invalidate
(C,W)I5 No action;
stay in invalid state.
(C,W)V5 No action;
go to invalid state.
CD5 No action (modified data
lost);
go to invalid state.
Cache
push
(C,W)I6
(C,W)I7
No action;
stay in invalid state.
(C,W)V6 No action;
go to invalid state.
CD6 Push modified line to
memory;
go to invalid state.
(C,W)V7 No action;
stay in valid state.
CD7 Push modified line to
memory;
go to valid state.
Table 4-8. Data Cache Line State Transitions (Current State Invalid)
Access Response
Read miss (C,W)I1 Read line from memory and update cache;
supply data to processor;
go to valid state.
Read hit (C,W)I2 Not possible
Write miss (copyback) CI3 Read line from memory and update cache;
write data to cache;
go to modified state.
Write miss (write-through) WI3 Write data to memory;
stay in invalid state.
Write hit (copyback) CI4 Not possible
Write hit (write-through) WI4 Not possible
Cache invalidate (C,W)I5 No action;
stay in invalid state.
Cache push (C,W)I6 No action;
stay in invalid state.
Cache push (C,W)I7 No action;
stay in invalid state.
Table 4-7. Data Cache Line State Transitions (Continued)
Access
Current State
Invalid (V = 0) Valid (V = 1, M = 0) Modified (V = 1, M = 1)