Datasheet

Chapter 5. Debug Support 5-3
Signal Descriptions
Figure 5-2 shows PSTCLK timing.
Figure 5-2. PSTCLK Timing
5.2.1 Processor Status/Debug Data (PSTDDATA[7:0])
Processor status data outputs are used to indicate both processor status and captured address
and data values. They operate at half the processor’s frequency. Given that real-time trace
information appears as a sequence of 4-bit data values, there are no alignment restrictions;
that is, the processor status (PST) values and operands may appear on either nibble of
PSTDDATA[7:0]. The upper nibble (PSTDDATA[7:4]) is the most significant.
CSR controls capturing of data values. Executing the WDDATA instruction captures data
displayed on PSTDDATA. These signals are updated each processor cycle and displayed
two values at a time for two processor clock cycles. Table 5-2 shows the PSTDDATA output
for the processor’s sequential execution of single-cycle instructions (A, B, C, D...). Cycle
counts are shown relative to processor frequency. These outputs indicate the current
processor pipeline status and are not related to the current bus transfer.
The signal timing for the example in Table 5-2 is shown in Figure 5-3.
Figure 5-3. PSTDDATA: Single-Cycle Instruction Timing
Table 5-2. PSTDDATA: Sequential Execution of Single-Cycle Instructions
Cycle PSTDDATA[7:0]
T {PST for A, PST for B}
T+1 {PST for A, PST for B}
T+2 {PST for C, PST for D}
T+3 {PST for C, PST for D}
T+4 {PST for E, PST for F}
T+5 {PST for E, PST for F}
PSTCLK
PSTDDATA
PSTDDATA
PSTCLK
{A, B} {C, D} {E, F}
PCLK