Datasheet
xvi
MCF5407 User’s Manual
CONTENTS
Paragraph
Number
Title
Page
Number
17.2.1.1 Address Bus (A[23:0]).............................................................................. 17-7
17.2.1.2 Address Bus (A[31:24]/PP[15:8]) ............................................................ 17-7
17.2.2 Data Bus (D[31:0]) ....................................................................................... 17-8
17.2.3 Read/Write (R/W
)......................................................................................... 17-8
17.2.4 Size (SIZ[1:0]) .............................................................................................. 17-8
17.2.5 Transfer Start (TS
) ........................................................................................ 17-9
17.2.6 Address Strobe (AS) ..................................................................................... 17-9
17.2.7 Transfer Acknowledge (T
A) ......................................................................... 17-9
17.2.8 Transfer In Progress (TIP
/PP7)................................................................... 17-10
17.2.9 Transfer Type (TT[1:0]/PP[1:0]) ................................................................ 17-10
17.2.10 Transfer Modifier (TM[2:0]/PP[4:2]/DACK[1:0])..................................... 17-10
17.3 Interrupt Control Signals................................................................................. 17-12
17.3.1 Interrupt Request (IRQ1
/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4, and IRQ7)....... 17-12
17.4 Bus Arbitration Signals................................................................................... 17-12
17.4.1 Bus Request (BR
) ....................................................................................... 17-12
17.4.2 Bus Grant (BG
).......................................................................................... 17-12
17.4.3 Bus Driven (BD)......................................................................................... 17-13
17.5 Clock and Reset Signals.................................................................................. 17-13
17.5.1 Reset In (RSTI
)........................................................................................... 17-13
17.5.2 Clock Input (CLKIN).................................................................................. 17-13
17.5.3 Bus Clock Output (BCLKO) ...................................................................... 17-13
17.5.4 Reset Out (RSTO)....................................................................................... 17-13
17.5.5 Data/Configuration Pins (D[7:0]) ............................................................... 17-14
17.5.5.1 D[7:5,3]—Boot Chip-Select (CS0
) Configuration ................................. 17-14
17.5.5.2 D7—Auto Acknowledge Configuration (AA_CONFIG) ...................... 17-14
17.5.5.3 D[6:5]—Port Size Configuration (PS_CONFIG[1:0])........................... 17-14
17.5.5.4 D3—Byte-Enable Configuration (BE_CONFIG) .................................. 17-15
17.5.6 D4—Address Configuration (ADDR_CONFIG) ....................................... 17-15
17.5.6.1 D[2:0]—Divide Control (DIVIDE[2:0]) ................................................ 17-15
17.6 Chip-Select Module Signals ........................................................................... 17-15
17.6.1 Chip-Select (CS[7:0]) ................................................................................. 17-15
17.6.2 Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) ............................ 17-16
17.6.3 Output Enable (OE) .................................................................................... 17-16
17.7 DRAM Controller Signals .............................................................................. 17-16
17.7.1 Row Address Strobes (RAS[1:0])............................................................... 17-16
17.7.2 Column Address Strobes (CAS[3:0]) ......................................................... 17-16
17.7.3 DRAM Write (DRAMW)........................................................................... 17-16
17.7.4 Synchronous DRAM Column Address Strobe (SCAS) ............................. 17-17
17.7.5 Synchronous DRAM Row Address Strobe (SRAS)................................... 17-17
17.7.6 Synchronous DRAM Clock Enable (SCKE) .............................................. 17-17
17.7.7 Synchronous Edge Select (EDGESEL) ...................................................... 17-17
17.8 DMA Controller Module Signals.................................................................... 17-17
17.8.1 DMA Request (DREQ[1:0]/PP[6:5]).......................................................... 17-17