Datasheet

5-8 MCF5407 User’s Manual

Programming Model

Two scenarios exist for data—0xFFFF_FFFF

• A B marker occurs on the left nibble of PSTDDATA with the data of 0xFF

following:

PSTDDATA[7:0]

0xBF

0xFF

0xFX (X indicates that the next PST value is guaranteed to not be 0xF.)

• A B marker occurs on the right nibble of PSTDDATA with the data of 0xFF

following:

PSTDDATA[7:0]

0xYB

0xFF

0xXY (X indicates the PST value is guaranteed not to be 0xF, and Y signiﬁes a

PSTDDATA value that doesn’t affect the 0xFF count.)

Thus, a count of either nine or more sequential single 0xF values or ﬁve or more sequential

0xFF values signiﬁes the HALT condition.

5.4 Programming Model

In addition to the existing BDM commands that provide access to the processor’s registers

and the memory subsystem, the debug module contains 19 registers to support the required

functionality. These registers are also accessible from the processor’s supervisor

programming model by executing the WDEBUG instruction. Thus, the breakpoint

hardware in the debug module can be accessed by the external development system using

the debug serial interface or by the operating system running on the processor core.

Software is responsible for guaranteeing that accesses to these resources are serialized and

logically consistent. Hardware provides a locking mechanism in the CSR to allow the

external development system to disable any attempted writes by the processor to the

breakpoint registers (setting CSR[IPW]). BDM commands must not be issued if the

MCF5407 is using the WDEBUG instruction to access debug module registers or the

resulting behavior is undeﬁned.

These registers, shown in Figure 5-5, are treated as 32-bit quantities, regardless of the

number of implemented bits.