Datasheet

5-10 MCF5407 User’s Manual
Programming Model
NOTE:
Debug control registers can be written by the external
development system or the CPU through the WDEBUG
instruction.
CSR is write-only from the programming model as debug
control register 0x00 using the supervisor-mode WDEBUG
instruction. It can be read from and written through the BDM
port using the
RDMREG and WDMREG commands.
5.4.1 Address Attribute Trigger Registers (AATR, AATR1)
The address attribute trigger registers (AATR, AATR1) define address attributes and a mask
to be matched in the trigger. The register value is compared with address attribute signals
from the processor’s local high-speed bus, as defined by the setting of the trigger definition
register (TDR) for AATR and the extended trigger definition register (XTDR) for AATR1.
0x07 Trigger definition register TDR 0x0000_0000 p. 5-18
0x08 Program counter breakpoint register PBR — p. 5-16
0x09 Program counter breakpoint mask register PBMR — p. 5-16
0x0A–0x0B Reserved — — —
0x0C Address breakpoint high register ABHR — p. 5-12
0x0D Address breakpoint low register ABLR — p. 5-12
0x0E Data breakpoint register DBR — p. 5-15
0x0F Data breakpoint mask register DBMR — p. 5-15
0x10–0x15 Reserved — — —
0x16 Address attribute trigger register 1 AATR1 0x0000_0005 p. 5-10
0x17 Extended trigger definition register XTDR 0x0000_0000 p. 5-19
0x18 Program counter breakpoint 1 register PBR1 0x0000_0000 p. 5-16
0x19 Reserved — — —
0x1A Program counter breakpoint register 2 PBR2 0x0000_0000 p. 5-16
0x1B Program counter breakpoint register 3 PBR3 0x0000_0000 p. 5-16
0x1C Address high breakpoint register 1 ABHR1 — p. 5-12
0x1D Address low breakpoint register 1 ABLR1 — p. 5-12
0x1E Data breakpoint register 1 DBR1 — p. 5-15
0x1F Data breakpoint mask register 1 DBMR1 — p. 5-15
Table 5-6. BDM/Breakpoint Registers (Continued)
DRc[4–0] Register Name Abbreviation Initial State Page