Datasheet

Chapter 5. Debug Support 5-11
Programming Model
Table 5-7 describes AATR and AATR1 fields.
1514131211109876543210
Field RM SZM TTM TMM R SZ TT TM
Reset 0000_0000_0000_0101
R/W AATR and AATR1 are accessible in supervisor mode as debug control register 0x06 and 0x16
respectively, and using the WDEBUG instruction and through the BDM port using the
WDMREG command.
DRc[4–0] 0x06 (AATR); 0x16 (AATR1)
Figure 5-6. Address Attribute Trigger Registers (AATR, AATR1)
Table 5-7. AATR and AATR1 Field Descriptions
Bits Name Description
15 RM Read/write mask. Setting RM masks R in address comparisons.
14–13 SZM Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.
12–11 TTM Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons.
10–8 TMM Transfer modifier mask. Setting a TMM bit masks the corresponding TM bit in address comparisons.
7 R Read/write. R is compared with the R/W
signal of the processor’s local bus.
6–5 SZ Size. Compared to the processor’s local bus size signals.
00 Longword
01 Byte
10 Word
11 Reserved
4–3 TT Transfer type. Compared with the local bus transfer type signals.
00 Normal processor access
01 Reserved
10 Emulator mode access
11 Acknowledge/CPU space access
These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding
indicates an external or DMA access (for backward compatibility). These bits affect the TM bits.
2–0 TM Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental
information for each transfer type.
TT = 00 (nor
mal mode):
000 Data and instruction cache line push
001 User data access
010 User code access
011 Instruction cache invalidate
100 Data cache push
101 Supervisor data access
110 Supervisor code access
111 INTOUCH instruction access
TT = 10 (em
ulator mode):
0xx–100 Reserved
101 Emulator mode data access
110 Emulator mode code access
111 Reserved
TT = 11 (ac
knowledge/CPU space transfers):
000 CPU space access
001–111 Interrupt acknowledge levels 1–7
These bits also define the TM encoding for BDM memory commands (for backward compatibility).