Datasheet
CONTENTS
Paragraph
Number
Title
Page
Number
Contents
xvii
17.8.2 Transfer Modifier/DMA Acknowledge (TM[2:0]/DACK[1:0]) ................ 17-18
17.9 Serial Module Signals..................................................................................... 17-18
17.9.1 Transmitter Serial Data Output (TxD)........................................................ 17-18
17.9.2 Receiver Serial Data Input (RxD)............................................................... 17-19
17.9.3 Clear to Send (CTS).................................................................................... 17-19
17.9.4 Request to Send (RTS) ............................................................................... 17-19
17.10 Timer Module Signals..................................................................................... 17-19
17.10.1 Timer Inputs (TIN[1:0]).............................................................................. 17-19
17.10.2 Timer Outputs (TOUT1, TOUT0) .............................................................. 17-19
17.11 Parallel I/O Port (PP[15:0]) ............................................................................ 17-19
17.12 I
2
C Module Signals......................................................................................... 17-20
17.12.1 I
2
C Serial Clock (SCL)............................................................................... 17-20
17.12.2 I
2
C Serial Data (SDA) ................................................................................ 17-20
17.13 Debug and Test Signals .................................................................................. 17-20
17.13.1 Test Mode (MTMOD[3:0]) ........................................................................ 17-20
17.13.2 High Impedance (HIZ
)................................................................................ 17-20
17.13.3 Processor Clock Output (PSTCLK)............................................................ 17-20
17.13.4 Processor Status Debug Data (PSTDDATA[7:0])...................................... 17-21
17.14 Debug Module/JTAG Signals......................................................................... 17-21
17.14.1 Test Reset/Development Serial Clock (TRST
/DSCLK) ............................ 17-21
17.14.2 Test Mode Select/Breakpoint (TMS/BKPT
) .............................................. 17-21
17.14.3 Test Data Input/Development Serial Input (TDI/DSI) ............................... 17-22
17.14.4 Test Data Output/Development Serial Output (TDO/DSO)....................... 17-22
17.14.5 Test Clock (TCK) ....................................................................................... 17-22
Chapter 18
Bus Operation
18.1 Features............................................................................................................. 18-1
18.2 Bus and Control Signals.................................................................................... 18-1
18.3 Bus Characteristics............................................................................................ 18-2
18.4 Data Transfer Operation ................................................................................... 18-2
18.4.1 Bus Cycle Execution..................................................................................... 18-4
18.4.2 Data Transfer Cycle States ........................................................................... 18-5
18.4.3 Read Cycle.................................................................................................... 18-7
18.4.4 Write Cycle ................................................................................................... 18-8
18.4.5 Fast-Termination Cycles............................................................................... 18-9
18.4.6 Back-to-Back Bus Cycles ........................................................................... 18-10
18.4.7 Burst Cycles................................................................................................ 18-11
18.4.7.1 Line Transfers......................................................................................... 18-12
18.4.7.2 Line Read Bus Cycles............................................................................. 18-12
18.4.7.3 Line Write Bus Cycles............................................................................ 18-14