Datasheet

5-16 MCF5407 User’s Manual
Programming Model
Table 5-12 describes DBRn fields.
Table 5-13 describes DBMRn fields.
DBRs support both aligned and misaligned references. Table 5-14 shows relationships
between processor address, access size, and location within the 32-bit data bus.
5.4.6 Program Counter Breakpoint/Mask Registers
(PBR, PBR1, PBR2, PBR3, PBMR)
Each PC breakpoint register (PBR, PBR1, PBR2, PBR3) defines an instruction address for
use as part of the trigger. These registers’ contents are compared with the processor’s
31 0
Field Data (DBR/DBR1); Mask (DBMR/DBMR1)
Reset Uninitialized
R/W DBR and DBR1 are accessible in supervisor mode as debug control register 0x0E and 0x1E, using the
WDEBUG instruction and through the BDM port using the
RDMREG and WDMREG commands.
DBMR and DBMR1 are accessible in supervisor mode as debug control register 0x0F and 0x0F1 using the
WDEBUG instruction and via the BDM port using the
WDMREG command.
DRc[4–0] 0x0E (DBR), 0x1E (DBR1); 0x0F (DBMR), 0x1F (DBMR1)
Figure 5-10. Data Breakpoint/Mask Registers (DBR/DBR1 and DBMR/DBMR1)
Table 5-12. DBRn Field Descriptions
Bits Name Description
31–0 Data Data breakpoint value. Contains the value to be compared with the data value from the processor’s
local bus as a breakpoint trigger.
Table 5-13. DBMRn Field Descriptions
Bits Name Description
31–0 Mask Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBRn bit allows
the corresponding DBRn bit to be compared to the appropriate bit of the processor’s local data bus.
Setting a DBMRn bit causes that bit to be ignored.
Table 5-14. Access Size and Operand Data Location
A[1:0] Access Size Operand Location
00 Byte D[31:24]
01 Byte D[23:16]
10 Byte D[15:8]
11 Byte D[7:0]
0x Word D[31:16]
1x Word D[15:0]
xx Longword D[31:0]