Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller FQFP 208 (28x28) 32-Bit 162 MHz I/O number 16

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Chapter 5. Debug Support 5-17

Programming Model

program counter register when the appropriate valid bit is set and TDR and/or XTDR are

conﬁgured appropriately. PBR bits are masked by clearing corresponding PBMR bits.

Results are compared with the processor’s program counter register, as deﬁned in TDR

and/or XTDR. PBR1–PBR3 are not masked. Figure 5-11 shows the PC breakpoint register.

Table 5-15 describes PBR, PBR1, PBR2, and PBR3 ﬁelds.

PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG

instruction and via the BDM port using the

WDMREG command. Figure 5-12 shows PBMR.

Table 5-16 describes PBMR ﬁelds.

31 10

Field Program Counter V

Reset — 0

R/W Write. PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and

through the BDM port using the

RDMREG and WDMREG commands using values shown in Section 5.5.3.3,

“Command Set Descriptions.”

DRc[4–0] 0x08 (PBR); 0x18 (PBR1); 0x1A (PBR2); 0x1B (PBR3)

PBR does not have a valid bit. PBR[0] is read as 0 and should be cleared.

Figure 5-11. Program Counter Breakpoint Registers (PBR, PBR1, PBR2, PBR3)

Table 5-15. PBR, PBR1, PBR2, PBR3 Field Descriptions

Bits Name Description

31–1 Address PC breakpoint address. The 31-bit address to be compared with the PC as a breakpoint trigger.

PBR does not have a valid bit.

0 V Valid. Breakpoint registers are compared with the processor’s program counter register when the

appropriate valid bit is set and TDR and/or XTDR are conﬁgured appropriately. This bit is not

implemented on PBR.

31 10

Field Mask —

Reset — —

R/W Write. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG

instruction and via the BDM port using the wdmreg command.

DRc[4–0] 0x09

Figure 5-12. Program Counter Breakpoint Mask Register (PBMR)

Table 5-16. PBMR Field Descriptions

Bits Name Description

31–0 Mask PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to

the appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.