Datasheet

Chapter 5. Debug Support 5-21
Programming Model
5.4.9 Resulting Set of Possible Trigger Combinations
The resulting set of possible breakpoint trigger combinations consist of the following
options where || denotes logical OR, && denotes logical AND, and {} denotes an optional
additional trigger term:
One-level triggers of the form:
if (PC_breakpoint)
if (PC_breakpoint||Address_breakpoint{&& Data_breakpoint})
if (PC_breakpoint||Address_breakpoint{&& Data_breakpoint}
|| Address1_breakpoint{&& Data1_breakpoint})
if (Address_breakpoint {&& Data_breakpoint})
if ((Address_breakpoint {&& Data_breakpoint})
|| (Address1_breakpoint{&& Data1_breakpoint}))
if (Address1_breakpoint {&& Data1_breakpoint})
Two-level triggers of the form:
if (PC_breakpoint)
then if (Address_breakpoint{&& Data_breakpoint})
if (PC_breakpoint)
then if (Address_breakpoint{&& Data_breakpoint}
|| Address1_breakpoint{&& Data1_breakpoint})
if (PC_breakpoint)
then if (Address1_breakpoint{&& Data1_breakpoint})
if (Address_breakpoint {&& Data_breakpoint})
then if (Address1_breakpoint{&& Data1_breakpoint})
if (Address1_breakpoint {&& Data1_breakpoint})
then if (Address_breakpoint{&& Data_breakpoint})
if (Address_breakpoint {&& Data_breakpoint})
then if (PC_breakpoint)
if (Address1_breakpoint {&& Data1_breakpoint})
21/5 DI Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the
DBR1 contents.
20–18/
4–2
EAx Enable address bits. Setting an EAx bit enables the corresponding address breakpoint. If all three
bits are cleared, this breakpoint is disabled.
20/4 EAI Enable address breakpoint inverted. Breakpoint is based outside the range between
ABLR1 and ABHR1.
19/3 EAR Enable address breakpoint range. Breakpoint is based on the range defined between
ABLR1 and ABHR1.
18/2 EAL Enable address breakpoint low. The breakpoint is based on the address in ABLR1.
17–16,
1–0
— Reserved, should be cleared.
Table 5-18. XTDR Field Descriptions (Continued)
Bits Name Description